Agilent Signal Integrity Seminar 2013

• How to characterize and debug high speed digital

links on your physical prototype?

• What part of your design is eating up your Eye

margins?

1

Agenda - How to characterize and debug high speed digital

links on your physical prototype – what part of your design

is eating up your Eye margins?

Where does eye mask come from (eg. Rx chip)

Symbol/ frame errors

Compare against Freq and jitter

Jitter tolerence curve (eg USB3)

Separating receiver test from the Tx/channel

TX RX Channel

Simplified Receiver Architecture

Rx latch

DLL

Rx

PLL

Receiver RX Data

Tx latch

Tx

DLL

Transmitter

DUT SerDes in

LoopBack Mode

TX Data

4

How do we ensure ‘Error Free’ operation?

How can we specify to the transmitter plus channel design the quality of the

signal that the receiver needs?

Answer - We need to measure the Receiver’s tolerance to jitter.

How to generate the Mask requirement?

5

Loopback Test Mode for Receiver test

A product‘s transmitter will send the same data as received by its receiver (not necessarily

the same bits).

Product Under Test

Receiver

Transmitter

Clock

Error Ratio

Compare

Pattern

Generator

Pattern

Error

Detector

Pattern

6

AGILENT SI Seminar 2012

by Pascal GRISON

Rx Minimum Eye Opening at BER=10E-12

Rx latch

DLL

Rx

PLL

ISI

Channel

Receiver RX Data

Semiconductor Vendors are Using Jbert to Characterize SERDES BER susceptibility

to ISI, Random Jitter and Frequency dependent Periodic Jitter Eye Closure

Tx latch

Tx

DLL

Transmitter

DUT SerDes in

LoopBack Mode

TX Data

JBERT up to 28Gb/s PRBS Generation

with Calibrated Jitter insertion

and integrated adjustable ISI channel

JBERT Realtime Error Detector allow

thorough BER Analysis and BER Eye

Opening

7

Page 8

Common Concepts in High Speed Serial Data

Interface Standards

• Bi-directional interface, i.e. each product has transmitter and receiver

• No common clock but clock recovery

• Data re-timing

• Data encoding (typically 8B/10B encoding)

• Test modes support for testing of transmitters and receivers

• Examples: USB 3.0 SuperSpeed interface, SATA, SAS, PCIe 2...

Host

Transmitter

Receiver

Device

Receiver

Transmitter

Channel

Clock

Clock

Page 9

8B/10B Encoding At A Glance

• 8 bit data is encoded into 10 bit symbols (Dx.y symbols)

• There are combinations of 10 bits which aren‘t a valid 10B symbol (>50%)

• DC-balance: each valid symbol has either an even number of ones and zeros or the

difference is 2

• For many symbols there are two valid codes:

the running disparity (=difference between transmitted 1s and 0s) determines which

encoding is picked based on the preceding symbols

• Control characters (K symbols) allow to mix commands and data on the same wire

• Comma characters allow to identify unambiguously the first bit of a 10 bit symbol in a data

stream. Only a subset of K symbols are commas (K28.1, K28.5, K28.7)

• High transition density: eases clock recovery as the maximum run-length is 5 bits

Check http://en.wikipedia.org/wiki/8B/10B for additional information on 8B/10B encoding

Page 10

8B/10B Data Encoding

0

1

2

3

4

5

6

7

K

8 Bits

Control or

data word 0

1

2

3

4

5

6

7

8

9

10 Bits

3B/4B

5B/6B

• 8B/10B separates into 5B/6B and 3B/4B encoding

• Mapping results in either one or two different codes for the 10B symbol

• Supports encoding of 12 control words (Kx.y) and 256 data words (Dx.y)

0‘

1‘

2‘

3‘

4‘

5‘

6‘

7‘

8‘

9‘

To be used

with

negative

disparity

To be used

with positive

disparity

D x . y

K x . y

Mostly

2 different

codes

Page 11

Comma Characters

• Commas are symbols that have five same bits in a row

There is no combination of symbols that could generate five same bits

• Comma symbols are used for synchronization

i.e. finding the alignment of 8B/10B codes within a bit-stream

• K28.1, K28.5, K28.7 are suitable comma symbols (most standards use K28.5)

0011111010

1100000101 K28.5

Symbol Lock

....010101010101010101010100111110100101010101010101....

compare

No symbol alignment found

Page 12

Possible Effects Due to Bit Errors

• A symbol may turn into a different symbol

• A symbol may turn into an illegal 10 bit string

• Some standards substitute illegal 10 bit codes (e.g. USB 3.0 uses K28.4)

• Also sometimes implementation specific

• The error could flip the running disparity

• All subsequent data could be coded with the new running disparity

• The error could violate the running disparity rules

In all cases a meaningful measure is to count one error only

Page 13

Illustration Of A Disparity Flip Caused By A Bit Error

• A single bit error at the receiver will cause the DUT to receive a different symbol and may

change the running disparity when being in loopback

Only a BERT which understands 8B/10B encoded symbols will show the correct

error count. A traditional BERT would show too many errors.

The screen shot shows a repeated D12.0, D11.4 pattern received/looped by a SATA drive. A

bit error in a D11.4 results in a D11.3 and flips the running disparity

Page 14

• In many standards there is no common clock. Therefore in a communication system each

product has its own oscillator

• Typical host/device configuration in USB 3.0, SATA, SAS, etc:

• Clock A and clock B will never be identical, often SSC is used

• The elastic buffer compensates the slight differences in data rate (i.e. performs re-timing):

Independent Clock Domains And Data Re-Timing

Device

Receiver

FF EQ

Loop-

back

Device

function

CDR

Transmitter

Host

Loop-

back Device

function

Receiver

FF EQ

CDR

Transmitter

Channel

Elastic

buffer

Elastic

buffer

Clock

B

Clock

A

Page 15

Device

Receiver

FF EQ

Loop-

back

Device

function

CDR

Transmitter

Host

Loop-

back Device

function

Receiver

FF EQ

CDR

Transmitter

Channel

Elastic

buffer

data-symbol

filler-primitive

Handling of Filler Primitives During Re-Timing

original data and filler symbols sent with fA

Retimed data with fB < fA

fB> fA

fB < fA If clock B is running slower symbols from the incoming data must be dropped. Therefore the incoming data

already contains filler primitives

fB> fA If clock B is faster filler primitives must be inserted to prevent the buffer from running empty

Elastic

buffer

Clock

B

Clock

A

Filler primitives are symbols in the data stream that carry no information

Page 16

Check your instrument before using it for receiver tests:

•Can it deal with fillers at arbitrary locations?

•Does its clock accuracy match the standard requirements?

Re-Timing Summarized

• Filler primitives are needed to compensate for differences in clock speed

• Filler primitives carry no information,

they can be inserted or removed at any location without changing anything

• SATA / SAS filler primitive is called Align,

USB 3.0 / PCIe filler primitive is called Skip

• Usually standards have a minimum filler occurrence requirement (e.g. every

256 dwords in SATA, every 384 dwords in USB 3.0) – this is based on clock

stability spec, SSC clock deviation and min buffer size requirement

Page 17

Re-Timing During Receiver Test Illustrated

Filler

primitive

removed

Filler

primitive

inserted

Page 18

Loopback Test Mode For Receiver Test

• A product‘s transmitter will send the same data as received by its receiver

(not necessarily the same bits)

Product Under Test

Receiver

Transmitter Clock

Error Ratio

Compare

Pattern

Generator

Pattern

Error

Detector

Pattern

Page 19

• Instrument sends proper 8B/10B encoded data with fillers and calibrated signal impairment

• Product under test will loop back data applying re-timing and unknown running disparity

Error Detection Challenge During

Receiver Test In Re-timing Architectures

Product under test

Receiver

Loop-

back

Device

function

FF

CDR

EQ

Transmitter

Elastic

buffer

Clock

Data-out with fBERT

D+ D- D+ F+ F+ D+ D- D+ Re-timed data with fProduct

D+ D- D+ F+ D+ D- D+

Clock

Loopback data with fproduct

and new disparity

D- D+ D- F- D- D+ D-

Page 20

Traditional

BERT

• Traditional BERTs cannot deal with retiming i.e. more or less bits

• Workaround: using same clock on BERT and product under test

• Problem: test coverage and there is no clock in- or output with SATA, SAS, USB,...

• Traditional BERTs cannot deal with changing running disparity (due to errors)

• Workaround: test only until the first error occurs

• Problem: low confidence in test results

Traditional BERTs Compare Only Bits

Product under test

Receiver

Loop-

back

Device

function

FF

CDR

EQ

Transmitter

Elastic

buffer

Clock

Data-out with fBERT

D+ D- D+ F+ F+ D+ D- D+

Clock

Output

Input

No re-timing

D+ D- D+ F+ F+ D+ D- D+

Loopback data with fBERT

but new disparity

D- D+ D- F- F- D- D+ D-

Page 21

• With Option A02 J-BERT error detector supports 8B/10B encoded data, and

can deal with re-timed data

RX Setup With J-BERT B Option A02

(SER / FER Support)

Product under test

Receiver

Loop-

back

Device

function

FF

CDR

EQ

Transmitter

Elastic

buffer

Clock

Data-out with fBERT

D+ D- D+ F+ F+ D+ D- D+

Expected data with fproduct

Loopback data with fproduct

and new disparity

Re-timed data with fProduct

D+ D- D+ F+ D+ D- D+

D- D+ D- F- D- D+ D-

D D D D D D

Clock

CDR

Characteristic eye closure by sinusoidal Jitter

BER Scan

Eye Diagram

22

Understanding the Jitter Mix given for Rx tolerance testing

* Refer to figure 6-19 of Universal Serial Bus 3.0 Specification

UI

MHz

1

0.2

4.9

f1

2

0.6

0.1

2 1 0.5

Rj = 0.17 UI (p-p)

Sj

Sj

Sj

Derived max Tj for Rx tolerance testing *

receiver compliance curve:

products must pass at all frequencies

5 compliance test points mentioned in

the standard

Sj

50

Sj

23

More SJ Frequencies to ensure compliance

Critical receiver Sj problem area

between 8MHz and 30MHz

Additional test point

recommendation:

• 10 MHz (f_3dB_PLL)

• 15 MHz (PLL peaking area)

• 20 MHz (identified as critical

frequency)

• 33 MHz (frequency typically

present in hosts) 0.1

1

10

100

0.01 0.1 1 10 100

Tota

l Jitte

r [U

I]

Sinusoidal Jitter Frequency [MHz]

Jitter Tolerance Example Measured at USB-IF Workshop #69, 9/15~9/17-2009

USB SuperSpeed Device

Max Passed Jitter

Min Spec

high freq. low freq.

PLL LBW

& peaking

24

USB 3.0 SuperSpeed Receiver Test Setup for Devices

Connect ions:

o Use DC blocking capacitors in the connection from the J-BERT / Deemphasis-Box output to the test

fixture input

o For host testing: Additional cabling and a BIAS tee are required

o All necessary connections are displayed in the N5990A software, too

DUT

N4903B

11742A

Blocking

Caps 11‘

Device Test Fixture 1

Device Test

Fixture 2

Short USB3

cable

3m USB3

cable

5V

use upper

Port

N4916B USB

25

USB 3 Loopback Training

27

Typical SuperSpeed Link Turn-on Sequence

28

USB3.0 Receiver Test Demo

Page 29

Rx Compliance and Jitter Tolerance Testing

31

Summary

• It is becoming increasingly important to include connector(s) and

tracking in the receiver path characterization.

• The receiver is specified by the minimum eye height and width

required for ‘Error Free’ reception.

• The jitter tolerance (eye width) is typically dependent on the

frequency of the jitter (more tolerant to low frequency jitter).

• Testing is simple with the right equipment.

• It is easy to lose margin if the pattern generator has uncontrolled

jitter components.

Page 32