September 2015

Advanced  Debug  for        SOC  Verifica6on  Tutorial  

[Indago™  Debug  Pla>orm  Overview]  

Debugging  Con6nues  to  be  the  Most  Time  Consuming  Effort  by  50%  

 

50%

10% 5%

10%

25%

Today’s Verification Effort

Debug

Coverage analysis

Test planning

Test creation

Test execution Source: Verification engineer survey by Cadence

!  Same Debug Methodology for 20 years While there has been very good progress in improving all other areas of verification, very little has been done in Debug automation

!  Increasingly larger SoC designs and many debug iterations producing Terabytes of Data

Finding the source of the bug is becoming like finding “a needle in a hay stack”

And it’s getting worse. WHY ???

What  would  you  do  if  you  were  given  25%  of  your  TIME  back?  

Cadence  set  out  to  do  exactly  that    

25%

25% TIME

Savings 10%

5%

10%

25%

Today’s Verification Effort after cutting Debug Time in ½

Debug

TIME Savings

Coverage analysis

Test planning

Test creation

Test execution

Common Debug Platform

!  Debug platform architected from the ground up Leveraging the latest in s/w database architecture as its foundation of a common framework for performance, extensibility, and scalability

But HOW ???

!  Patented Root Cause Analysis (RCA) Technology and BIG Data Techniques Leverage patented RCA technology together with BIG Data techniques to quickly find the source of the bug

Common Debug Platform

!  Platform extensibility, scalability, and integration User-selected Apps covering various functional verification tasks to view and debug from IP-to-SoC level across functional teams

… and more to come

Introducing  Cadence®  Indago™    Debug  Pla>orm  

Finding  the  Source  of  the  Bug  a7er  One  Debug  Run  is  NO  Longer  a  Dream  Database Debug Sim Code

Traditional Debug Flow

DB Debug Sim Code

Debug Sim Code

Time savings*

DB

DB DB

Leveraging BIG Data concepts and RCA

Waveforms only

Indago™ Debug Flow

Waveforms, log messages, code execution – “Big Data”

Iteration 1

Duplicate data collected every iteration

Iteration 2 Iteration …N

“Cadence’s Indago Debug Analyzer App has improved our debug productivity up to 50 percent because it helps us find the root cause of the bugs faster with features like reverse debugging. We believe the Indago Debug Platform will enable us to continue to deliver for applications including consumer electronics, fitness tracking, wearables and IoT.” Robert Richter, Senior Expert, ASIC Development, at Bosch

2x - 3x DEBUG PRODUCTIVITY

As seen by customers

*When following the prescribed methodology

•  2X  debug  produc6vity  improvement  with  Indago  through:    

–  Patented  Root  Cause  Analysis  technology  –  BIG  Data  concepts  for  intelligent  automa6on  –  Integrated  Analysis  GUI  scalable  from  IP-­‐to-­‐SoC  level  debug  

 •  3  Indago  pla>orm  Apps  addressing  specific  debug  

tasks  –  Debug  Analyzer:    RTL/GL  and  Testbench  –  Embedded  So[ware  Debug:    Synchronized  ESW/HW  –  Protocol  Debug:    Interface  protocol  func6onal  valida6on  

 

•  Supports  Cadence  and  3rd  party  verifica6on  engines  –  Debug  Analyzer:    Phased  RTL/TB  support  through  next  

several  releases  –  Embedded  SW:    Today  (unmodified  TARMAC  trace  files)  –  Protocol  Debug:  Today  (for  supported  protocols)  

Key  Benefits  of  Cadence®  Indago™  Debug  Pla>orm  

A  Paradigm  Shi7  in  Debug  Methodology  CuBng  Debug  Time  in  ½    

Indago Debug Platform

Indago Debug

Analyzer

Indago Embedded SW Debug

Indago Protocol Debug

RTL/GL

•  Compe6tors  provide  RCA  on  RTL/GL  design  only  –  RTL  only  one  piece  of  the  debug  picture  

•  Engineers  are  forced  to  debug  with  severely  limited  visibility  into  other  aspects  of  the  environment    

Compe6tors  Debug  Solu6ons    RCA  on  RTL  Only  

Testbench

Embedded SW

SystemC/C/C++

VIP

VIP

VIP

VIP

Waveform/debug DB (RCA)

Text Logs

Embedded SW DB Waveform DB

RTL/GL

SystemC

Embedded SW

Testbench

Causal Relationships to explore

Jump to RC of value changes

Indago™  Root  Cause  Analysis  RCA  across  all  aspects  of  the  simula6on  

RCA Engines

Debug DB VIP DB

TB/RTL Source Execution

DB

Messaging DB

Messaging DB

Embedded SW DB

VIP DB

TB/RTL Source Execution

DB

Waveform DB

RTL/GL SystemC

Embedded SW

Testbench

Debug DB

Causal Relationships to explore

Jump to RC of value changes

Indago™  Root  Cause  Analysis  RCA  across  all  aspects  =  increased  recording  

 

RCA Engines

Messaging DB

Embedded SW DB

VIP DB

TB/RTL Source Execution

DB

Waveform DB

RTL/GL SystemC

Embedded SW

Testbench

Debug DB

Indago Big Data (when compared to traditional debug)

Indago™  Root  Cause  Analysis  RCA  across  all  aspects  =  increased  recording  

 

–  Root  Cause  Analysis  (RCA)  •  RCA  Component  •  Direct  Access  

–  Playback  Debugger  –  SmartLog  –  SmartPrint    –  Time  Tables  –  Powerful  Searching  –  Call  stack  analysis  –  Variables  Table  

•  Let’s  take  a  closer  look  at  some  of  these  features  now  …  

Indago™  Big  Data  Analysis  What  makes  Indago  unique  

•  Recording  addi6onal  data  allows  for  powerful  analysis  capabili6es  such  as:    

•  Debug  data  from  all  sources  visualized  in  the  same  GUI  

Indago™  Debug  Pla>orm    Unified  Analysis  GUI  

Messaging DB

Embedded SW DB

VIP DB

Waveform DB

RTL/GL SystemC

Embedded SW

Testbench

TB/RTL Source Execution

DB

–  Eliminates  GUI  context  switching  

–  Consistent  debug  experience  

–  Quick  ramp  up    

–  Unified  RCA  across  debug  data  sources  

–  Complete  synchroniza6on  

–  App  specific  customiza6on    

Debug DB

•  Apps  are  individual  products  targeted  at  a  specific  debug  task  –  Indago  Debug  Analyzer  App:    RTL/GL/TB  debug  –  Indago  Embedded  SW  Debug  App:    Embedded  SW/HW  Debug    

–  Indago  Protocol  Debug  App:    Debug  of  Verifica6on  IP  Protocol  Traffic  

Indago™  Apps  

Indago Debug Platform

Indago Debug

Analyzer App

Indago Embedded SW Debug

App

Indago Protocol Debug

App

IndagoTM  Debug  Analyzer  App  DEMO  

pass parity other

•  Ran a regression of 100 test on the “CLAB” project •  Overall 25 tests failed •  14 tests failed on parity mismatch error •  Picked the shortest parity mismatch test to debug

Demo Scenario

pass  

fail  

•  Mixed VHDL and Verilog design •  System Verilog VE •  Three input interfaces

–  Serial packets IF (drives packets byte by byte) –  Parallel packets IF (drives packets in one cycle) –  Register IF (used for configuring the DUT)

•  One output interface –  Multi packets IF (drives packets in one cycle

with parity)

Demo environment Basics (CLAB)

Failing Scenario

 In  FIFO  

 In  FIFO  

In    Mux  

Muter   Limiter   Parity  

Out  Mux  

Out  FIFO  

Out  FIFO  

Inverter  

Muter   Limiter   Parity  

Registers  

32

8

32 Arbiter  

8

Parallel IF

Serial IF

Multi IF

UVM  Scoreboard        

Add Predict Match

Parallel packet

Multi packet

Parallel packet driven DUT Parity calculation

Expected Parity calculation Parity Mismatch

•  VE developer debugging •  In this session

–  Understand the what random configuration was generated

–  Explore the VE parity calculation –  Explore the DUT parity calculation –  Compare the 2 parity algorithms –  Assign session to designer upon DUT bug

Demo debug Objectives

IndagoTM  Embedded  So;ware  Debug  App  DEMO  

•  Unified  embedded  so[ware  debug  for  all  Cadence  pla>orms  •  Unified  embedded  so[ware  debug  for  all  processor  

abstrac6ons  –  Fast  processor  models  ,  RTL  (simula6on),  RTL  (emula6on)  

•  Post-­‐process  (now)  and  interac6ve  so[ware  debug  (future)  

•  Mul6-­‐core  and  mul6-­‐processor  •  Hardware/so[ware  co-­‐debug  •  Bare  metal  to  OS  so[ware  debug  

Unified  Embedded  So;ware  Debug  Across  PlaCorms  and  Processor  Model  AbstracEons  

Unified Embedded Software Debug Engine

Palladium®

Verification CompuEng Platform (Emula'on)

SoC Interconnect Fabric

Display

INTC Timer

CSI DSI

UART

GPU Memory Controller

SATA USB3 …

Peripheral Fabric

USB2 Ethernet

UARTs Timers

Interrupt Manager

TLM / RTL Bridge

Router

CPU Sub-system RTL I/F

Reset Manager

TLM Memory

TLM/RTL Hybrid

CST

ARM Processor Fast Model

DDR for RTL

TLM/RTL Hybrids (Virtual  Prototype    

with  RTL)

AMBA Interconnect Fabric

Display

INTC Timer

CSI DSI

UART

GPU Memory Controller

SATA USB3

…

USB2

Ethernet

DDR for RTL

RTL ARM Processor Incisive®

Functional Verification

Platform (Simula'on)

Indago  ESWD  App  Flow  

Simulation or Emulation

ARM Processor

core ARM

Tarmac

ARM Processor

core ARM

Tarmac

Tarmac log

Tarmac log

SW image

SW image

SW images

for processors

Embedded Software Debug Engine

Indago Database

Indago Embedded Software Debug App

1. Compile and Run

2. Generate Database Respond to Queries

3. Debug Offline

Rest of the D

esign

Waveform Database

CCI-­‐400  or  Customer  CCI  

       

A53  Cluster  

   

   

MALI  or  Customer  

GPU  

   

S4   S2   S1   S0  ADB   ADB  

ADB  

GIC-­‐400  

NIC-­‐400    

 PCIe  RC    

LCD  DMA  V8  Mobile    Example    System  

NIC-­‐400  (2x1)  

ADB  

NIC-­‐400

 

ADB   ADB  

 TZC-­‐400  

DMC-­‐400  or  Customer    DDR  Controller  

F0  F1  F2  F3  

On-­‐Chip  ROM  

SRAM  

Video  SRAM  

#2  #4  

L2  Cache  

   

Customer  DMA      

ADB  

#1  #3  

Timers  

UART  UART  UART  UART0,1,2,3  

NIC-­‐400    NIC-­‐400  

IP   IP   IP  IP  IP  

DVFS  CLK/PSO  Domain  

CLK/PSO  Domain  

 System  Control  Processor  

 

Coherent  Masters  

Non-­‐Coherent  Masters  

IP  

ADB   ADB  

ADB  

DEMO  Design  :    HAMSA  SoC  –  CPU  Subsystem  

•  Environment:    –  4  ARM  A53  Cores    –  Several  Peripherals,  including  4  UART  Interfaces  

•  Failing  Scenario:    –  Each  core  should  write  an  output  message  through  its  

corresponding  UART  interface  to  signify  that  boo6ng  is  complete  –  We  are  receiving  character  ‘C’  twice  on  UART3  (scoreboard  test  in  

testbench  would  catch  this)  –  We  are  not  receiving  any  message  from  CPU2  on  the  UART2  

interface  

•  To  Debug:    –  Examine  HDL  signals  –  Examine  Embedded  SW  code  execu6on  –  Single  step    –  Examine  func6ons  and  variables  values  

Embedded  SW  Debug  Scenario  

•  Simplifies  debug  by  illumina6ng  design  and  VIP  behavior  •  Support  for  many  popular  protocols  in  2015,  others  to  follow  •  Seamless  integra6on  with  all  major  simulators    

Smart Log

Channel Viewer

Life Story

State Machine Viewer

Indago™ Protocol Debug App Next-­‐genera6on  protocol  debug  aid  

 

ü   2X  debug  produc6vity  improvement  •  Indago  Debug  Pla>orm  CUTS  Your  DEBUG    TIME  in  HALF  

•  Gain  more  TIME  back  in  your  LIFE  •  Customers*  are  seeing  these  benefits  today!  

 

ü   3  Apps  addressing  specific  debug  tasks  •  RTL/GL  and  Testbench  •  Synchronized  ESW/HW  •  Interface  protocol  func6onal  valida6on  •  More  Apps  to  come  

 ü   Available  Today!  

Summary:  New  Cadence®  Indago™  Debug  Pla>orm    

*Customers like Renesas, Siemens, and TI presented about their success at CDNLive. ST has a success story published on Cadence.com.