accurate leakage/delay estimation for finfet standard cells under pvt variations using the response...

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Accurate Leakage/Delay Estimation for FinFET Standard Cells underPVT Variations using the Response Surface Methodology

SOURINDRA M. CHAUDHURI, PRATEEK MISHRA, andNIRAJ K. JHA, Princeton University

Among different multi-gate transistors, FinFETs and Trigate FETs have set themselves apart as the mostpromising candidates for the upcoming 22nm technology node and beyond owing to their superior deviceperformance, lower leakage power consumption, and cost-effective fabrication process. Innovative circuitdesign and optimization techniques will be required to harness the power of multi-gate transistors, whichin turn will depend on accurate leakage and timing characterization of these devices under spatial andenvironmental variations. Hence, in order to aid circuit designers, we present accurate analytical modelsusing central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimatethe leakage current and delay of FinFET standard cells under the effect of variations in gate length (LG), finthickness (TSI), gate-oxide thickness (TOX), gate-workfunction (�G), supply voltage (VDD), and temperature(T ). To the best of our knowledge, this is the first such attempt to develop analytical models for leakage/delayestimation of FinFET logic gates. To derive these models, we employ TCAD device simulations of adjusted 2Ddevice cross sections that have been shown to track TCAD device simulations of 3D device behavior withina 1–3% error range. This drastically reduces the CPU time of our modeling technique (by several orders ofmagnitude) without much loss in accuracy. We present analytical leakage and delay models for different sizesand logic styles (e.g., shorted-gate (SG) and independent-gate (IG) FinFETs at the 22nm technology node).Both leakage and delay estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results (QMC simulations track the accuracy of Monte Carlo simulations,but are several orders of magnitude faster) obtained for different adjusted-2D logic gates with a root meansquare error (RMSE) in the 0.23%–5.87% range.

Categories and Subject Descriptors: I.6.5 [Simulation and Modeling]: Model Development

General Terms: Design, Algorithms, Performance

Additional Key Words and Phrases: FinFETs, non-planar devices, leakage/delay models

ACM Reference Format:Sourindra M. Chaudhuri, Prateek Mishra, and Niraj K. Jha. 2014. Accurate leakage/delay estimation forFinFET standard cells under PVT variations using the response surface methodology. ACM J. Emerg. Tech-nol. Comput. Syst. 11, 2, Article 19 (November 2014), 20 pages.DOI: http://dx.doi.org/10.1145/2665066

1. INTRODUCTION

Multi-gate transistors [Nowak et al. 2004], for example, FinFETs and Trigate FETs,have begun replacing conventional MOSFETs owing to their smaller subthresholdleakage, superior gate control over the channel, and reduced sensitivity to processvariations. Initially, the cost and complexity associated with fabrication were the pri-mary challenges in making these devices the industry driver. These are no longer

The conference version of this work was published in Proceedings of VLSI Design.This work was supported by the SRC under contract no. 2010-HJ-2079.Authors’ addresses: S. M. Chaudhuri (corresponding author), P. Mishra, and N. K. Jha, ElectricalEngineering Department, Princeton University, Princeton, NJ, 08544; corresponding author’s email:[email protected] to make digital or hard copies of all or part of this work for personal or classroom use is grantedwithout fee provided that copies are not made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. Copyrights for components of this work owned byothers than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, topost on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissionsfrom [email protected]© 2014 ACM 1550-4832/2014/11-ART19 $15.00

DOI: http://dx.doi.org/10.1145/2665066

ACM Journal on Emerging Technologies in Computing Systems, Vol. 11, No. 2, Article 19, Pub. date: November 2014.

19:2 S. M. Chaudhuri et al.

Fig. 1. A typical n/p-FinFET device.

critical, as the key players in the semiconductor industry have managed to fabricatethese devices at roughly the same cost and with minor modifications to the conven-tional CMOS fabrication process. Superior performance, significantly lower leakage,and low fabrication cost are the main reasons behind recent adoption of these devicesby various companies.

In this article, we focus on FinFETs, which are a promising variant among differentmulti-gate transistors explored so far. A silicon-on-insulator (SOI) FinFET is a struc-ture with a thin vertical silicon fin placed on an insulating base and surrounded bymetal gates (Figure 1). The top gate is separated from the channel by placing a thickspacer material in between, which makes it a double-gate structure. By eliminatingthe spacer, the structure can be transformed into a Trigate device. The ratio of fin bodythickness (TSI) to gate length (LG) is usually kept small to ensure tighter control overthe channel by the gate. To address the problem of random dopant fluctuations, dopingin the channel region is typically maintained at a very low level (close to undoped).FinFETs can be operated in different modes: shorted-gate (SG) and independent-gate(IG). In the SG mode of operation, the front and back gates are electrically connected todeliver maximum gate drive, whereas in the IG mode, the top of the FinFET is etchedaway to make the gates independent so that they can be biased to different values.In the IG mode of operation, back-gate bias can be used to alter the threshold voltage(Vth) of the front gate. This is very useful in reducing the off current, that is, leakagecurrent (ILEAK), of the transistor.

Though FinFETs can deliver superior performance at a lower leakage and similarcost relative to CMOS, they are still susceptible to process and environmental varia-tions. As FinFETs become mainstream, characterizing their leakage and timing willbecome essential for circuit design and optimization. The key challenge in character-izing a FinFET is its complex structure, which requires much longer processing timescompared to traditional MOSFETs. However, we have shown that it is possible to findequivalent adjusted 2D cross sections of FinFETs that closely (error within 1–3%) track3D device behavior and remain valid even under process-voltage-temperature (PVT)variations [Chaudhuri and Jha 2014]. We still need to characterize leakage and timingbehavior of FinFET logic gates under the influence of PVT variations, and adjusted2D cross sections can make this job significantly easier. The key contributions of thisarticle are as follows.

—Since LG, TSI , TOX, and �G have been shown to have a significant impact on ILEAKand on-current (ION) [Mishra et al. 2010], we consider variations in these parametersalong with VDD to develop leakage and delay models for 1× and 2× inverter (INV)and NAND gate implemented in SG and IG modes of operation using CCRD basedon RSM.


Accurate Leakage/Delay Estimation for FinFET Standard Cells 19:3

—Instead of simulating complete 3D devices, we deploy CCRD on adjusted 2D cross-sections of FinFET devices, which provide accuracy close to that obtained from 3Ddevice simulation, yet in several orders of magnitude less time (the time reducesfrom CPU days to minutes).

—Then we develop leakage and delay analytical models to capture the effect of tem-perature for different-size INVs and NAND gates operated in the SG or IG mode.

—We show that the leakage and delay estimates obtained from the RSM-based modelsunder process-voltage (PV) variations are in close agreement (maximum testingRMSE of 1.97% and 4.69%, respectively) with the QMC [Singhee and Rutenbar2007] simulation results for adjusted-2D FinFET logic gates.

—Finally, we show that the combined PVT variation-aware leakage models incur amaximum testing RMSE of only 5.87%. Since delay of FinFET logic gates is notimpacted much by temperature, we only derive PV variation-aware delay models forthem.

The rest of the article is organized as follows. In Section 2, we review related work.In Section 3, we give a detailed description of the simulation setup. In Section 4, wediscuss design of experiments used for modeling leakage/delay in FinFET logic gates.In Section 5, we discuss validation of our models. Finally, in Section 6, we conclude.

2. RELATED WORK

The promise of multi-gate transistors has motivated researchers to explore the im-pact of these devices at the circuit level. Research has already been done on ob-taining different leakage-delay trade-offs based on the SG/IG modes of operation[Chiang et al. 2005; Kumar et al. 2004; Tawfik and Kursun 2007; Mishra et al. 2009]. Tooptimize power of FinFET circuits, gate sizing and multiple supply/threshold voltageshave been established as effective strategies [Mishra et al. 2009; Ouyang and Xie 2008;Swahn and Hassoun 2006; Muttreja et al. 2007]. Use of �G has been recommended tocontrol device Vth under process variations [Xiong and Bokor 2003]. The dependence ofILEAK on device temperature has also been investigated [Ananthan and Roy 2006; Guet al. 2008; Choi et al. 2007]. Response-surface-based methodology has been proposedearlier for modeling effect of process variations on CMOS circuit delay [Bhat et al.2007].

Researchers have developed a quasi-3D numerical model to simulate modern Fin-FET structures [Shao and Yu 2005]. This model accounts for ballistic transport alongthe channel. It yields very accurate results for devices with gate length below 10nmbecause it is developed based on non-equilibrium Green’s function. LG, TSI , TOX, and�G have been shown to be critical in determining device behavior under process vari-ations [Mishra et al. 2010]. The leakage-delay spectrum has been explored for variousFinFET standard cells [Bhoj and Jha 2013], however, not under process variations.Simulations run on a fully self-consistent 3D quantum transport simulator show aclear discrepancy between 2D and 3D simulation of a FinFET device [Khan et al.2008]. Hence, work has been done to bridge this accuracy gap between 3D and 2Dsimulations [Chaudhuri and Jha 2014] through adjustment of 2D cross sections.

3. SIMULATION SETUP

Our simulation platform uses Python scripts to integrate Sentaurus TCAD Struc-ture Editor, device simulator, Inspect [Synopsys 2011], and MATLAB to ease dataflowamong all these tools. It also automates mixed-mode device simulation to estimate leak-age/delay of FinFET standard logic cells under PVT variations. MATLAB and Pythonscripts are used to postprocess the output, develop analytical models using CCRD, andvalidate them against QMC simulations.



Fig. 2. Simulation flow.

Fig. 3. 3D nFinFET device created by the Struc-ture Editor.

Fig. 4. 2D (X-Y) cross section of the 3D nFinFETdevice.

Figure 2 shows the simulation flow in detail. First, Sentaurus TCAD StructureEditor generates 2D FinFET structures with the corrective gate underlap (discussedahead) that helps track 3D device behavior. Then this 2D FinFET structure, alongwith a custom parameter file that sets values for all physical model parameters and acommand file with simulation instructions, is given as input to the Sentaurus TCADDevice, which performs mixed-mode simulation to obtain leakage/delay estimates. Theoutput files containing leakage/delay data are then further processed in MATLAB.

We target SG and IG FinFET logic gates implemented in the 22nm SOI FinFET tech-nology. Figure 3 shows a 3D nFinFET and Figure 4 its 2D cross-section. Heavily-dopedextended source and drain regions are identified by (HCON × LCON). They eventu-ally terminate at the undoped channel region. The figure also makes it apparent thatthe doping concentration decreases gradually instead of changing in an abrupt fashion.This gives rise to a region near both edges of the gate, which is referred to as gate-source/drain underlap (LU N). For high-performance logic, a �G of 4.4eV (4.8eV) is used for thenFinFET (pFinFET) and a back gate bias of −0.2V for IG-mode simulations [Mishraet al. 2010].



Table I. FinFET Device Parameter Values

Parameter name (Unit) ValueLGF , LGB (nm) 20

TOXF , TOXB (nm) 1TSI (nm) 11

HF IN (nm) 40HGF , HGB (nm) 34

LSPF , LSPB (nm) 12.5LU N (nm) 10FP (nm) 60

NBODY (cm−3) 1016

�G (eV ) nFET: 4.4, pFET: 4.8NSD (cm−3) 1020

VDD (V ) 0.9

Table II. Adjusted LU N Pairs for Individual FinFETs [Chaudhuri and Jha 2014]

Mode Device Unadjusted LU N (nm) Adjusted LU N pair (nm)

SGnFinFET(1×) 10 (9.52, 8.74)nFinFET(2×) 10 (9.57, 8.74)pFinFET(1×) 10 (9.50, 8.56)pFinFET(2×) 10 (9.56, 8.60)pFinFET(4×) 10 (9.60, 8.56)

IGnFinFET(1×) 10 (9.36, 9.02)nFinFET(2×) 10 (9.40, 9.02)pFinFET(1×) 10 (9.40, 8.64)pFinFET(2×) 10 (9.46, 8.80)pFinFET(4×) 10 (9.50, 8.80)

Table I provides the values assumed for different physical parameters that describea typical n/pFinFET at the 22nm technology node. These values are based on thosepresented in the literature [Guillorn 2008; Wu et al. 2010; Yamashita et al. 2011] thatare calibrated based on data from the foundries. In our prior work [Chaudhuri andJha 2014], we have also presented ID versus VG curves that are in agreement withthose presented in the literature. Referring to Figure 4, the process parameters arefront physical gate length (LGF), back physical gate length (LGB), front gate oxide thick-ness (TOXF), back gate oxide thickness (TOXB), front gate thickness (HGF), back gatethickness (HGB), front gate spacer thickness (LSPF), back gate spacer thickness (LSPB),and LU N. WNEFF and WPEFF denote the effective widths of an nFinFET and pFinFET,respectively, and are defined as 2nHF IN (where n is the number of fins in the FinFETand HF IN is the fin height) for an SG FinFET and nHF IN for an IG FinFET. Theseeffective widths take into account both the front and back inversion channels formedin a typical FinFET. Other device parameters are body doping (NBODY ), source/draindoping (NSD), fin pitch (FP) that denotes the minimum distance required between themidpoint of two adjacent fins, and operating voltage (VDD).

For all our simulations, we consider bandgap narrowing models, the Philips-unifiedmodel for carrier mobility, and Shockley-Read-Hall and band-to-band tunneling mod-els to accurately capture the effect of carrier recombination [Synopsys 2011]. Table IIidentifies the adjusted LU N pairs (one for ILEAK and the other for ION) for SG and IGdevices (2× represents a device with two fins), which have been shown to effectivelycapture 3D device behavior [Chaudhuri and Jha 2014]. For accurate delay calculations,



Table III. Internal Capacitance (Cint) Comparison ofVarious 3D vs. 2D Logic Gates [Chaudhuri and Jha 2014]

Mode Logic gate 3D Cint ( f F) 2D Cint ( f F)

SGINV(1×) 0.378 0.277INV(2×) 0.736 0.497

NAND(1×) 0.326 0.212NAND(2×) 0.590 0.369

IGINV(1×) 0.227 0.150INV(2×) 0.429 0.284

NAND(1×) 0.351 0.248NAND(2×) 0.667 0.471

we also have to take into account the fact that the internal capacitance (Cint) of the logicgate is lower when using the 2D device model compared to the 3D device model, sincecapacitance is related to device structure. The internal capacitances can be obtainedfrom the 3D and 2D models of the logic gates by obtaining their delay under differentload capacitances and then solving for the internal capacitance. Table III shows the3D versus 2D internal capacitance values of different logic gates operating in SG andIG modes. Using this table, we adjust the load capacitances while running delay simu-lations for different logic gates using adjusted 2D cross sections. Hence, to accuratelyestimate the gate delay of the 3D model from its 2D cross section, we have to compen-sate for the reduced capacitance in the 2D model, along with the changed on-currentvia LU N adjustment. Table III presents adjusted values for INVs and NAND gates only.However, similar experiments can be performed for other logic gates as well to obtainLU N adjustments. We use CCRD on these adjusted cross-sections to model leakage anddelay under PVT variations.

4. DESIGN OF EXPERIMENT (DOE)

To develop analytical leakage/delay models for FinFET logic gates under PV variations,a wide variety of DOEs are possible. In this work, we rely on CCRD based on RSMto develop such models for the SG/IG inverter (SG/IG-INV) and SG/IG NAND gate(SG/IG-NAND). We develop leakage/delay models under PV variations for both 1×and 2× size logic gates. DOE first determines the most influential input parametersthrough screening of all available input parameters, and then analyzes the combinedinfluence of those important input parameters on the output. DOEs can be dividedinto three main categories: screening, full factorial, and response surface [Mutlu andRahman 2005], with varying efficiencies in covering the design space.

The screening design eliminates less important input parameters to reduce the de-sign space, thus compromising accuracy. In the full factorial design, each input vari-able can have multiple levels, thus significantly increasing problem complexity. Theresponse surface design usually combines different statistical and mathematical meth-ods to model engineering problems. It optimizes a response surface characterized byvarious input parameters and determines its dependence on those parameters. Thenumber of levels employed for each input variable is based on the dimension of themodel under consideration. Though both full factorial and response surface designyield highly accurate results because of their conservative nature, they become im-practical for higher-order models that depend on a large number of input variables. Inthis work, we consider quadratic models. For modeling a quadratic response surface,each variable needs to have three levels. Thus, for a t-variable design, the total numberof experiments required is 3t, which makes this procedure impractical for large t.

CCRD addresses the problems just discussed. It was first proposed by Box andWilson and further improved by Hunter et al. [1978]. It is geometrically demonstrated



Fig. 5. CCRD for t = 3.

Table IV. Relationship between Coded and ActualVariable Values

Code Actual value of variable−β xmin

−1 [(xmax + xmin)/2] − [(xmax − xmin)/2α]0 [(xmax + xmin)/2]

+1 [(xmax + xmin)/2] + [(xmax − xmin)/2α]+β xmax

Table V. Process and Voltage Parameters of SG/IG Logic Gates (1×/2×)along with Their Levels for CCRD

Coded variable levelLowest Low Center High Highest

Process parameter −β −1 0 +1 +β

LG (nm) 18 19.29 20 20.71 22TSI (nm) 10.0 10.65 11.0 11.35 12.0TOX (nm) 0.9 0.96 1.0 1.04 1.1�Gn (eV ) 4.38 4.393 4.40 4.407 4.42�Gp (eV ) 4.78 4.793 4.80 4.807 4.82VDD (V ) 0.81 0.87 0.90 0.93 0.99

in Figure 5. It includes a center point, six axial points, and eight factorial cube points.Hence, for a t-variable design, the total number of experiments required is 2t + 2t + 1,which can be reduced by replacing the factorial portion of the design with fractionalfactorial [NIST 2011]. The inclusion of factorial and axial points helps generate thelinear and quadratic terms, respectively. To maintain a constant variation of the modelfrom the design center, axial points are chosen in such a fashion that they allowrotatability. After determining the range of variation in input parameters, typicallyassumed to be around ±10% [Choi et al. 2007; Mishra et al. 2010] of their meanvalues, we encode them as ±1 for factorial points, ±β for axial points, and 0 for thecenter point. To take into account process variations in �G, a variation of ±10% in|�G −�S| is actually considered, where �S represents the workfunction of the intrinsicsemiconductor material. �S is 4.6eV. Table IV summarizes all the formulas used tocalculate the corresponding values of the encoded CCRD levels, where the minimum(maximum) value is represented by xmin (xmax) [Aslan 2008]. The value of α is calculatedusing the formula α = 2t/4. To model leakage and delay under PV variations in a FinFETlogic gate (e.g., INV/NAND), we consider six input variables: LG, TSI , TOX, �Gn, �Gp,and VDD, with full factorial CCRD. Hence, the total number of experiments requiredfor logic gates is 2t + 2t + 1 = 77 (t = 6) with the value of α = 2.83. The values fordifferent levels of CCRD input variables are summarized in Table V for both SG andIG modes of operation. In Table VI, we summarize the values of all input variables



Table VI. Coded Process and Voltage Parameters along with Their Actual Valuesfor all Logic Gates

Code LG TSI TOX �Gn �Gp VDD

−1 −1 −1 −1 −1 −1 19.29 10.65 0.96 4.393 4.793 0.87−1 −1 −1 −1 −1 1 19.29 10.65 0.96 4.393 4.793 0.93−1 −1 −1 −1 1 −1 19.29 10.65 0.96 4.393 4.807 0.87−1 −1 −1 −1 1 1 19.29 10.65 0.96 4.393 4.807 0.93−1 −1 −1 1 −1 −1 19.29 10.65 0.96 4.407 4.793 0.87−1 −1 −1 1 −1 1 19.29 10.65 0.96 4.407 4.793 0.93−1 −1 −1 1 1 −1 19.29 10.65 0.96 4.407 4.807 0.87−1 −1 −1 1 1 1 19.29 10.65 0.96 4.407 4.807 0.93−1 −1 1 −1 −1 −1 19.29 10.65 1.04 4.393 4.793 0.87−1 −1 1 −1 −1 1 19.29 10.65 1.04 4.393 4.793 0.93−1 −1 1 −1 1 −1 19.29 10.65 1.04 4.393 4.807 0.87−1 −1 1 −1 1 1 19.29 10.65 1.04 4.393 4.807 0.93−1 −1 1 1 −1 −1 19.29 10.65 1.04 4.407 4.793 0.87−1 −1 1 1 −1 1 19.29 10.65 1.04 4.407 4.793 0.93−1 −1 1 1 1 −1 19.29 10.65 1.04 4.407 4.807 0.87−1 −1 1 1 1 1 19.29 10.65 1.04 4.407 4.807 0.93−1 1 −1 −1 −1 −1 19.29 11.35 0.96 4.393 4.793 0.87−1 1 −1 −1 −1 1 19.29 11.35 0.96 4.393 4.793 0.93−1 1 −1 −1 1 −1 19.29 11.35 0.96 4.393 4.807 0.87−1 1 −1 −1 1 1 19.29 11.35 0.96 4.393 4.807 0.93−1 1 −1 1 −1 −1 19.29 11.35 0.96 4.407 4.793 0.87−1 1 −1 1 −1 1 19.29 11.35 0.96 4.407 4.793 0.93−1 1 −1 1 1 −1 19.29 11.35 0.96 4.407 4.807 0.87−1 1 −1 1 1 1 19.29 11.35 0.96 4.407 4.807 0.93−1 1 1 −1 −1 −1 19.29 11.35 1.04 4.393 4.793 0.87−1 1 1 −1 −1 1 19.29 11.35 1.04 4.393 4.793 0.93−1 1 1 −1 1 −1 19.29 11.35 1.04 4.393 4.807 0.87−1 1 1 −1 1 1 19.29 11.35 1.04 4.393 4.807 0.93−1 1 1 1 −1 −1 19.29 11.35 1.04 4.407 4.793 0.87−1 1 1 1 −1 1 19.29 11.35 1.04 4.407 4.793 0.93−1 1 1 1 1 −1 19.29 11.35 1.04 4.407 4.807 0.87−1 1 1 1 1 1 19.29 11.35 1.04 4.407 4.807 0.93

1 −1 −1 −1 −1 −1 20.71 10.65 0.96 4.393 4.793 0.871 −1 −1 −1 −1 1 20.71 10.65 0.96 4.393 4.793 0.931 −1 −1 −1 1 −1 20.71 10.65 0.96 4.393 4.807 0.871 −1 −1 −1 1 1 20.71 10.65 0.96 4.393 4.807 0.931 −1 −1 1 −1 −1 20.71 10.65 0.96 4.407 4.793 0.871 −1 −1 1 −1 1 20.71 10.65 0.96 4.407 4.793 0.931 −1 −1 1 1 −1 20.71 10.65 0.96 4.407 4.807 0.871 −1 −1 1 1 1 20.71 10.65 0.96 4.407 4.807 0.931 −1 1 −1 −1 −1 20.71 10.65 1.04 4.393 4.793 0.871 −1 1 −1 −1 1 20.71 10.65 1.04 4.393 4.793 0.931 −1 1 −1 1 −1 20.71 10.65 1.04 4.393 4.807 0.871 −1 1 −1 1 1 20.71 10.65 1.04 4.393 4.807 0.931 −1 1 1 −1 −1 20.71 10.65 1.04 4.407 4.793 0.871 −1 1 1 −1 1 20.71 10.65 1.04 4.407 4.793 0.931 −1 1 1 1 −1 20.71 10.65 1.04 4.407 4.807 0.87

Continued



Table VI. Continued

Code LG TSI TOX �Gn �Gp VDD

1 −1 1 1 1 1 20.71 10.65 1.04 4.407 4.807 0.931 1 −1 −1 −1 −1 20.71 11.35 0.96 4.393 4.793 0.871 1 −1 −1 −1 1 20.71 11.35 0.96 4.393 4.793 0.931 1 −1 −1 1 −1 20.71 11.35 0.96 4.393 4.807 0.871 1 −1 −1 1 1 20.71 11.35 0.96 4.393 4.807 0.931 1 −1 1 −1 −1 20.71 11.35 0.96 4.407 4.793 0.871 1 −1 1 −1 1 20.71 11.35 0.96 4.407 4.793 0.931 1 −1 1 1 −1 20.71 11.35 0.96 4.407 4.807 0.871 1 −1 1 1 1 20.71 11.35 0.96 4.407 4.807 0.931 1 1 −1 −1 −1 20.71 11.35 1.04 4.393 4.793 0.871 1 1 −1 −1 1 20.71 11.35 1.04 4.393 4.793 0.931 1 1 −1 1 −1 20.71 11.35 1.04 4.393 4.807 0.871 1 1 −1 1 1 20.71 11.35 1.04 4.393 4.807 0.931 1 1 1 −1 −1 20.71 11.35 1.04 4.407 4.793 0.871 1 1 1 −1 1 20.71 11.35 1.04 4.407 4.793 0.931 1 1 1 1 −1 20.71 11.35 1.04 4.407 4.807 0.871 1 1 1 1 1 20.71 11.35 1.04 4.407 4.807 0.93

−β 0 0 0 0 0 18.00 11.00 1.00 4.40 4.80 0.90β 0 0 0 0 0 22.00 11.00 1.00 4.40 4.80 0.900 −β 0 0 0 0 20.00 10.00 1.00 4.40 4.80 0.900 β 0 0 0 0 20.00 12.00 1.00 4.40 4.80 0.900 0 −β 0 0 0 20.00 11.00 0.90 4.40 4.80 0.900 0 β 0 0 0 20.00 11.00 1.10 4.40 4.80 0.900 0 0 −β 0 0 20.00 11.00 1.00 4.38 4.80 0.900 0 0 β 0 0 20.00 11.00 1.00 4.42 4.80 0.900 0 0 0 −β 0 20.00 11.00 1.00 4.40 4.78 0.900 0 0 0 β 0 20.00 11.00 1.00 4.40 4.82 0.900 0 0 0 0 −β 20.00 11.00 1.00 4.40 4.80 0.810 0 0 0 0 β 20.00 11.00 1.00 4.40 4.80 0.990 0 0 0 0 0 20.00 11.00 1.00 4.40 4.80 0.90

at different levels for all the required experiments to model leakage/delay in SG/IG-INV and SG/IG-NAND. We chose INV and NAND gates because they can be used toimplement any arbitrary logic circuit. However, the method is easily extensible to otherlogic gates as well.

4.1. RSM-Based Leakage/Delay Models under PV Variations

We have now defined all the necessary components required for CCRD based on RSM.RSM-based models are typically quadratic in predictor variables, which denote a validrelationship between the response variable and different predictor levels. A typicalRSM polynomial can be realized as

Yi = β0 + β1 Xi + β2 Xi Xj + ε, (1)

where Xi ’s are the predictor variables that predict the response variable Yi. This isachieved by finding the coefficients of regression (e.g., β0, β1, and β2), with ε being thepredictor noise. Regression analysis generally finds these coefficients by minimizing εover the whole sample space. We performed this analysis with the help of MATLAB 7.0.Since leakage in a FinFET device or logic gate has been observed to be exponentiallydependent on process parameters [Mishra et al. 2010], Yi represents ln(ILEAK) with



Table VII. RSM ln(ILEAK) Model Coefficients for SG-INV in Two Sizes

Coefficient valuesSG-INV1× SG-INV2×

Variable 0-ln(ILEAK) 1-ln(ILEAK) 0-ln(ILEAK) 1-ln(ILEAK)const 616.4932 300.1944 574.2884 198.8053

x1 1.7640 −2.2384 1.7206 −2.1517x2 −3.8144 4.4614 −3.6995 4.4408x3 −16.9040 17.8675 −16.6460 17.6001x4 −106.2174 −118.0142 −93.6594 −96.3875x5 −130.9793 −65.7473 −124.6780 −43.2027x6 −7.2759 3.8946 −7.7712 3.7526

x1.x2 −0.0189 −0.0212 −0.0181 −0.0241x1.x3 −0.0709 −0.0787 −0.0681 −0.0994x1.x4 −0.4494 0.0001 −0.4459 0.0000x1.x5 0.0000 0.4091 0.0000 0.4144x1.x6 −0.0921 −0.0930 −0.0908 −0.0912x2.x3 0.0807 0.0825 0.0675 0.1286x2.x4 0.9412 −0.0003 0.9370 0.0000x2.x5 0.0000 −0.8399 0.0000 −0.8371x2.x6 0.1411 0.1609 0.1395 0.1604x3.x4 3.9925 −0.0025 3.9844 0.0000x3.x5 0.0000 −3.5292 0.0000 −3.4644x3.x6 0.5656 0.6653 0.5537 0.6617x4.x5 −0.0005 −0.0145 −0.0004 −0.0001x4.x6 1.6138 0.0034 1.7518 0.0000x5.x6 0.0000 −0.9080 0.0000 −0.8338x12 0.0092 0.0111 0.0096 0.0095x22 0.0128 0.0111 0.0082 0.0119x32 0.4732 0.4642 0.4097 0.3880x42 7.4830 13.4186 6.0433 10.9532x52 13.6439 10.9689 12.9875 8.5813x62 0.4163 0.4554 0.3578 0.3306

ILEAK measured in ampere. Tables VII, VIII, IX, X, XI, and XII show the coefficientsobtained for input vector dependent leakage models of size 1× and 2× SG/IG-INVand SG/IG-NAND, where x1, x2, x3, x4, x5, and x6, respectively, represent LG, TSI ,TOX, �Gn, �Gp, and VDD. The coefficients are reported up to four decimal places, andanything less significant than that is shown as 0. Similarly, delay models are presentedin Tables XIII and XIV. Delay dependence on process parameters is not exponential innature. Hence, in these tables, Yi represents delay (tD) measured in ps.

4.2. Quadratic Leakage Models under Temperature (T) Variations

In this section, we develop simple quadratic leakage models for logic gates of differentsizes under temperature variations. A typical quadratic polynomial can be realized as

Yi = β0 + β1 Xi + β2 X2i + ε. (2)

In this case, Yi is leakage (normalized to the value obtained at T = 300K) of alogic gate, and Xi is the temperature. As in the case of PV parameters, leakage variesexponentially with temperature. Hence, Yi represents ln(ILEAKn), where ILEAKn is thenormalized leakage factor under temperature variation. To develop leakage models, wechose 11 uniformly distributed points in the 300–398K range. Tables XV, XVI, XVII,XVIII, XIX, and XX show the coefficients obtained for input vector dependent leakage



Table VIII. RSM ln(ILEAK) Model Coefficients for IG-INV in Two Sizes

Coefficient valuesIG-INV1× IG-INV2×

Variable 0-ln(ILEAK)(*1e3) 1-ln(ILEAK) 0-ln(ILEAK) 1-ln(ILEAK)const 1.4975 −50.2581 521.8562 −163.9082

x1 0.0008 −1.0725 0.5366 −1.3746x2 −0.0010 1.7596 −1.3825 1.9934x3 −0.0089 3.9389 −13.3681 11.8263x4 −0.3410 −49.0711 −94.7984 −25.3268x5 −0.2875 20.6388 −104.6412 44.7154x6 −0.0082 −1.3368 −2.7840 3.3329

x1.x2 0.0000 0.0084 −0.0027 0.0056x1.x3 −0.0001 −0.0337 −0.0558 −0.0528x1.x4 −0.0003 0.0000 −0.2388 0.0000x1.x5 0.0000 0.0723 0.0000 0.1530x1.x6 −0.0001 −0.0424 −0.0651 −0.0462x2.x3 0.0000 −0.0355 0.0733 −0.0020x2.x4 0.0004 0.0000 0.4767 0.0000x2.x5 0.0000 −0.1513 0.0000 −0.1983x2.x6 0.0001 0.0276 0.1210 0.0529x3.x4 0.0018 0.0000 3.1989 0.0000x3.x5 0.0000 −0.3953 0.0000 −1.9282x3.x6 0.0007 0.5911 0.4987 0.4468x4.x5 0.0000 0.0000 −0.0003 0.0000x4.x6 0.0014 0.0000 0.6520 0.0000x5.x6 0.0000 0.4730 0.0000 −0.4134x12 0.0000 0.0112 0.0104 0.0105x22 0.0000 −0.0276 −0.0135 −0.0279x32 0.0016 0.1547 0.3816 −0.0385x42 0.0347 5.5763 6.4322 2.8781x52 0.0300 1.4576 10.9003 −0.9226x62 0.0016 0.0460 0.1594 −0.2184

models of size 1× and 2× SG/IG-INV and SG/IG-NAND, where x1 represents T . Delayof a logic gate does not vary much with temperature. Hence, we only develop leakagemodels under temperature variations. We have only modeled 1× and 2× gates becauseof limits on computational resources. However, the method can be extended to logicgates of any size.

5. VALIDATION OF LEAKAGE/DELAY MODELS

We next validate the leakage/delay models presented in the previous section by com-paring the results obtained from these models against QMC simulation results basedon adjusted-2D devices, which are efficient at tracking 3D results.

5.1. Validation of Leakage/Delay Models under PV Variations

In this section, we first validate the RSM-based leakage/delay models developed tocapture the effect of PV variations against QMC simulation. For QMC simulationof adjusted-2D logic gates, we considered 1,000 combinations of values for the in-put variables based on the concept of Sobol sequence, which ensures that points areevenly distributed in the testing space. This method, which is primarily based on low-discrepancy sequences, is known to converge quickly with much fewer samples relative



Table IX. RSM ln(ILEAK) Model Coefficients for SG-NAND1×Coefficient values

Variable 00-ln(ILEAK) 01-ln(ILEAK) 10-ln(ILEAK) 11-ln(ILEAK)const −2.0816 −2.6005 −2.5868 308.8780

x1 0.0002 0.0015 0.0014 −2.2108x2 −0.0002 −0.0028 −0.0027 4.8928x3 −0.0007 −0.0120 −0.0114 17.6969x4 0.1182 0.3426 0.3366 −120.7935x5 0.0878 0.0985 0.0983 −65.2475x6 2.2316 2.2380 2.2377 7.6680

x1.x2 0.0000 0.0000 0.0000 −0.0218x1.x3 0.0000 0.0000 0.0000 −0.0820x1.x4 0.0000 −0.0003 −0.0003 −0.0054x1.x5 0.0000 0.0000 0.0000 0.4086x1.x6 0.0000 0.0000 0.0000 −0.0911x2.x3 0.0000 0.0000 0.0000 0.0744x2.x4 0.0001 0.0006 0.0006 −0.0167x2.x5 0.0000 0.0000 0.0000 −0.8502x2.x6 0.0000 0.0000 0.0000 0.1783x3.x4 0.0003 0.0028 0.0027 0.1647x3.x5 0.0000 0.0001 0.0001 −3.5744x3.x6 0.0000 0.0001 0.0001 0.5027x4.x5 −0.0002 −0.0012 −0.0012 −0.0105x4.x6 −0.0004 −0.0017 −0.0017 −1.1685x5.x6 0.0000 −0.0001 −0.0001 −0.9543x12 0.0000 0.0000 0.0000 0.0113x22 0.0000 0.0000 0.0000 −0.0050x32 −0.0003 −0.0004 −0.0004 0.4939x42 −0.0133 −0.0383 −0.0376 13.9241x52 −0.0091 −0.0097 −0.0097 10.9400x62 −0.6209 −0.6210 −0.6210 1.0249

Fig. 6. 2D-QMC vs. model-based leakage distributions for SG/IG-INV under PV variations.



Table X. RSM ln(ILEAK) Model Coefficients for SG-NAND2×Coefficient values

Variable 00-ln(ILEAK) 01-ln(ILEAK) 10-ln(ILEAK) 11-ln(ILEAK) (*1e3)const −2.0863 −2.6346 −2.6263 −3.5343

x1 0.0002 0.0015 0.0014 −0.0021x2 −0.0002 −0.0030 −0.0029 0.0066x3 −0.0007 −0.0123 −0.0117 0.0264x4 0.1199 0.3544 0.3497 0.6857x5 0.0882 0.1022 0.1022 0.8164x6 2.2316 2.2382 2.2420 −0.1467

x1.x2 0.0000 0.0000 0.0000 0.0000x1.x3 0.0000 0.0000 0.0000 −0.0001x1.x4 0.0000 −0.0003 −0.0003 0.0000x1.x5 0.0000 0.0000 0.0000 0.0004x1.x6 0.0000 0.0000 0.0000 0.0001x2.x3 0.0000 0.0000 0.0000 0.0000x2.x4 0.0001 0.0007 0.0006 −0.0001x2.x5 0.0000 0.0000 0.0000 −0.0009x2.x6 0.0000 0.0000 0.0000 −0.0002x3.x4 0.0003 0.0029 0.0027 0.0001x3.x5 0.0000 0.0001 0.0001 −0.0036x3.x6 0.0000 0.0001 0.0001 −0.0011x4.x5 −0.0002 −0.0012 −0.0012 0.0000x4.x6 −0.0004 −0.0018 −0.0027 −0.0005x5.x6 0.0000 −0.0001 −0.0001 −0.0038x12 0.0000 0.0000 0.0000 0.0000x22 0.0000 0.0000 0.0000 −0.0001x32 −0.0003 −0.0004 −0.0004 −0.0028x42 −0.0135 −0.0396 −0.0390 −0.0777x52 −0.0091 −0.0101 −0.0101 −0.0806x62 −0.6209 −0.6210 −0.6209 0.1034

Fig. 7. 2D-QMC vs. model-based leakage distributions for SG-NAND under PV variations.



Table XI. RSM ln(ILEAK) Model Coefficients for IG-NAND1×Coefficient values

Variable 00-ln(ILEAK) 01-ln(ILEAK) 10-ln(ILEAK) 11-ln(ILEAK) (*1e3)const −2.0116 −2.1498 −2.1200 2.7182

x1 0.0001 0.0004 0.0003 −0.0013x2 0.0000 −0.0007 −0.0005 0.0025x3 0.0004 −0.0024 −0.0014 0.0077x4 0.0870 0.1412 0.1284 −0.6576x5 0.0874 0.0954 0.0946 −0.5752x6 2.2303 2.2328 2.2321 0.0051

x1.x2 0.0000 0.0000 0.0000 0.0000x1.x3 0.0000 0.0000 0.0000 0.0000x1.x4 0.0000 −0.0001 −0.0001 0.0000x1.x5 0.0000 0.0000 0.0000 0.0001x1.x6 0.0000 0.0000 0.0000 0.0000x2.x3 0.0000 0.0000 0.0000 0.0001x2.x4 0.0000 0.0002 0.0001 0.0000x2.x5 0.0000 0.0000 0.0000 −0.0005x2.x6 0.0000 0.0000 0.0000 0.0001x3.x4 0.0001 0.0006 0.0004 0.0003x3.x5 0.0000 0.0000 0.0000 −0.0024x3.x6 0.0000 0.0000 0.0000 0.0001x4.x5 −0.0001 −0.0008 −0.0006 0.0000x4.x6 −0.0001 −0.0006 −0.0004 −0.0031x5.x6 0.0000 −0.0001 −0.0001 0.0001x12 0.0000 0.0000 0.0000 0.0000x22 0.0000 0.0000 0.0000 0.0000x32 −0.0003 −0.0004 −0.0003 0.0020x42 −0.0098 −0.0156 −0.0143 0.0752x52 −0.0091 −0.0096 −0.0096 0.0641x62 −0.6209 −0.6209 −0.6209 0.0044

Table XII. RSM ln(ILEAK) Model Coefficients for IG-NAND2×Coefficient values

Variable 00-ln(ILEAK) 01-ln(ILEAK) 10-ln(ILEAK) 11-ln(ILEAK) (*1e4)const −2.0096 −2.1323 −2.1050 3.0481

x1 0.0001 0.0004 0.0003 0.0014x2 0.0000 −0.0007 −0.0005 0.0034x3 0.0004 −0.0024 −0.0011 0.0269x4 0.0867 0.1377 0.1278 −0.6454x5 0.0868 0.0911 0.0887 −0.6878x6 2.2303 2.2328 2.2319 −0.0791

x1.x2 0.0000 0.0000 0.0000 0.0000x1.x3 0.0000 0.0000 0.0000 0.0000x1.x4 0.0000 −0.0001 −0.0001 −0.0002x1.x5 0.0000 0.0000 0.0000 −0.0002x1.x6 0.0000 0.0000 0.0000 0.0004x2.x3 0.0000 0.0000 0.0000 0.0001x2.x4 0.0000 0.0002 0.0001 −0.0005x2.x5 0.0000 0.0000 0.0000 −0.0005x2.x6 0.0000 0.0000 0.0000 0.0008x3.x4 0.0001 0.0006 0.0004 −0.0042x3.x5 0.0000 0.0001 0.0000 −0.0043x3.x6 0.0000 0.0000 0.0001 0.0068x4.x5 −0.0001 −0.0008 −0.0004 0.0241x4.x6 −0.0001 −0.0006 −0.0005 0.0053x5.x6 0.0000 −0.0001 0.0000 0.0057x12 0.0000 0.0000 0.0000 0.0000x22 0.0000 0.0000 0.0000 0.0000x32 −0.0003 −0.0003 −0.0003 0.0026x42 −0.0098 −0.0152 −0.0143 0.0614x52 −0.0090 −0.0091 −0.0090 0.0620x62 −0.6209 −0.6209 −0.6209 0.0034



Table XIII. RSM tD Model Coefficients for 1× SG/IG Logic Gates

tD Coefficient values (*1e-08)Variable SG-INV SG-NAND IG-INV IG-NAND

const 0.2692 0.3631 0.2197 5.7730x1 0.0002 0.0001 0.0010 0.0010x2 0.0002 −0.0001 −0.0027 −0.0090x3 −0.0006 −0.0019 0.0143 0.0400x4 −0.0606 −0.0817 0.0307 −1.3940x5 −0.0565 −0.0745 −0.1067 −1.0790x6 −0.0054 −0.0064 −0.0575 −0.1780

x1.x2 0.0000 0.0000 0.0000 0.0000x1.x3 0.0000 0.0000 0.0000 0.0000x1.x4 0.0000 0.0000 0.0001 0.0000x1.x5 0.0000 0.0000 −0.0002 0.0000x1.x6 0.0000 0.0000 −0.0002 0.0000x2.x3 0.0000 0.0000 −0.0001 0.0000x2.x4 0.0000 0.0000 −0.0003 0.0000x2.x5 0.0000 0.0000 0.0007 0.0010x2.x6 0.0000 0.0000 0.0004 0.0010x3.x4 0.0002 0.0001 0.0011 −0.0010x3.x5 −0.0001 0.0003 −0.0018 −0.0070x3.x6 −0.0001 −0.0003 −0.0018 −0.0030x4.x5 0.0007 −0.0003 −0.0006 0.0210x4.x6 −0.0008 −0.0014 −0.0072 −0.0050x5.x6 0.0015 0.0021 0.0159 0.0340x12 0.0000 0.0000 0.0000 0.0000x22 0.0000 0.0000 0.0000 0.0000x32 0.0002 0.0002 −0.0041 0.0040x42 0.0066 0.0096 −0.0022 0.1470x52 0.0055 0.0076 0.0093 0.0990x62 0.0009 0.0015 0.0061 0.0180

Fig. 8. 2D-QMC vs. model-based leakage distributions for IG-NAND under PV variations.



Table XIV. RSM tD Model Coefficients for 2× SG/IG Logic Gates

tD Coefficient values (*1e-08)Variable SG-INV SG-NAND IG-INV IG-NAND

const 0.1193 0.2963 0.1422 −1.0700x1 0.0000 0.0002 0.0109 −0.0070x2 0.0002 0.0001 0.0071 −0.0160x3 −0.0001 −0.0023 0.0965 0.1570x4 −0.0240 −0.0666 −0.0138 0.2490x5 −0.0274 −0.0616 −0.0725 0.3350x6 −0.0027 −0.0058 −0.2938 −0.4400

x1.x2 0.0000 0.0000 0.0000 0.0000x1.x3 0.0000 0.0000 −0.0001 0.0000x1.x4 0.0000 0.0000 −0.0009 0.0010x1.x5 0.0000 0.0000 −0.0014 0.0000x1.x6 0.0000 0.0000 0.0006 0.0000x2.x3 0.0000 0.0000 0.0001 −0.0010x2.x4 0.0000 0.0000 −0.0004 0.0040x2.x5 0.0000 0.0000 −0.0012 0.0000x2.x6 0.0000 0.0000 0.0011 0.0020x3.x4 0.0001 0.0002 −0.0116 −0.0150x3.x5 −0.0001 0.0003 −0.0081 −0.0130x3.x6 −0.0001 −0.0001 0.0013 −0.0110x4.x5 0.0005 0.0002 −0.0126 0.0600x4.x6 −0.0007 −0.0007 0.0185 0.0580x5.x6 0.0010 0.0014 0.0401 0.0330x12 0.0000 0.0000 0.0000 0.0000x22 0.0000 0.0000 0.0000 0.0000x32 0.0001 0.0002 −0.0032 −0.0030x42 0.0025 0.0076 0.0105 −0.0730x52 0.0025 0.0062 0.0146 −0.0650x62 0.0005 0.0010 −0.0042 0.0030

Table XV. ln(ILEAKn) Model Coefficients under T Variations for SG-INV in Both Sizes

Coefficient valuesSG-INV1× SG-INV2×

Variable 0-ln(ILEAKn) 1-ln(ILEAKn) 0-ln(ILEAKn) 1-ln(ILEAKn)const −19.84 −23.24 −19.81 −23.16

x1 0.0932 0.1087 0.0931 0.1083x12 −0.0001 −0.0001 −0.0001 −0.0001

Table XVI. ln(ILEAKn) Model Coefficients under T Variations for IG-INV in Both Sizes

Coefficient valuesIG-INV1× IG-INV2×


x1 0.1102 0.1256 0.1094 0.1260x12 −0.0001 −0.0001 −0.0001 −0.0001

Table XVII. ln(ILEAKn) Model Coefficients under T Variations for SG-NAND1×Coefficient values


x1 0.0988 0.0939 0.0934 0.1088x12 −0.0001 −0.0001 −0.0001 −0.0001



Table XVIII. ln(ILEAKn) Model Coefficients under T Variations for SG-NAND2×Coefficient values


x1 0.0987 0.0938 0.0933 0.1087x12 −0.0001 −0.0001 −0.0001 −0.0001

Table XIX. ln(ILEAKn) Model Coefficients under T Variations for IG-NAND1×Coefficient values


x1 0.1148 0.1104 0.1101 0.1255x12 −0.0001 −0.0001 −0.0001 −0.0001

Table XX. ln(ILEAKn) Model Coefficients under T Variations for IG-NAND2×Coefficient values


x1 0.1150 0.1097 0.1106 0.1256x12 −0.0001 −0.0001 −0.0001 −0.0001

Table XXI. Testing ILEAK/tD RMSE for SG/IG FinFET Logic Gates

Inverter NANDMode/gate 0-ILEAK 1-ILEAK tD 00-ILEAK 01-ILEAK 10-ILEAK 11-ILEAK tD

SG 0.76% 0.82% 0.29% 0.45% 0.77% 0.74% 0.96% 0.23%IG 1.68% 1.47% 4.69% 1.51% 1.68% 1.72% 1.97% 2.56%

Fig. 9. 2D-QMC vs. model-based delay distributions for SG/IG-INV/NAND under PV variations.



Fig. 10. 2D-QMC vs. model-based leakage distributions for SG/IG-INV under PVT variations.

Fig. 11. 2D-QMC vs. model-based leakage distributions for SG-NAND under PVT variations.

to complete Monte Carlo simulation [Singhee and Rutenbar 2007]. To test the leak-age/delay models developed for logic gates, we varied LG, TSI , TOX, �Gn, �Gp, and VDDsimultaneously. We assume that all input variables are normally distributed. The leak-age/delay distributions derived from such QMC simulations show excellent agreementwith the distributions obtained from the RSM based PV variation models for SG/IG-INV/NAND, as shown in Figures 6, 7, 8, and 9, respectively. Table XXI shows that thetesting RMSE is at most 0.96% (4.69%) for gates based on SG (IG) FinFETs. Due to



Fig. 12. 2D-QMC vs. model-based leakage distributions for IG-NAND under PVT variations.

the highly CPU-intensive (CPU weeks) nature of QMC simulations, we show resultsfor 1× logic gates only.

5.2. Validation of Leakage Models under PVT Variations

In this section, we validate the combined RSM-based PV and quadratic T models usedto calculate leakage of a logic gate. To show this, we again consider 1,000 combinationsof values of input variables based on the Sobol sequence. We assume that all inputvariables are normally distributed except T. For each combination, we choose the Tvalue randomly. Figures 10, 11, and 12 show a good agreement for SG/IG-INV/NAND.The maximum testing RMSE is limited to 5.87%.

Although the errors are small, they could be reduced further by going from aquadratic model to a cubic model. However, this would require 3t + 3t + 1 = 748(t = 6) experiments with CCRD, compared to 77 required for the quadratic model. Thiswould entail a huge increase in computational complexity for generating and validat-ing the models. Our quadratic macromodels generate leakage/delay distributions ofSG/IG FinFET logic gates with reasonable accuracy within fraction of a second andmake QMC simulations (adjusted-2D/3D), which may take CPU weeks, unnecessary.

6. CONCLUSIONS

In this article, we presented an efficient modeling technique for accurately estimatingleakage/delay in FinFET standard cells under PVT variations. We used adjusted 2Dcross sections of FinFETs that are good at tracking actual 3D device behavior withina 1–3% error range. This makes the proposed approach highly economical in terms ofsimulation time. The leakage/delay models developed under PVT variations use CCRDbased on RSM, which significantly minimizes the number of experiments required, buthave errors within a 0.23%–5.87% error range relative to accurate QMC simulations.Thus, our approach is both efficient and accurate.

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Received January 2014; revised May 2014; accepted August 2014


accurate leakage/delay estimation for finfet standard cells under pvt variations using the response...

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