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AccuCore Static Timing Analysis
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AccuCore Static Timing Analysis
ß High Performance SoC Timing Solution
ß Levels of Design Abstraction
ß History of Digital Functional Verification
ß Definitions of Key STA Terminology
ß Key capabilities of AccuCore Block-level STA
ß Key Capabilities of Full Chip STA
ß Using AccuCore STA in a Standalone Flow
ß Using AccuCore STA in a Unified Flow
ß Basic AccuCore STA Operations
ß Advanced Topics not in this Courseß STA and Worst Case Process Corners
ß Dynamic Logic (Domino)
ß Clock Skew Analysis
ß Tri-state bus characterization
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High Performance SoC Timing Solution
Full-ChipStatic Timing Analysis
Block/Core Characterizationand Static Timing Analysis
Cell Characterization
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Static Timing Analysis and Characterization inYour Design Flow
Custom Block Design
Simucad supports a bottoms-uptiming strategy to ensureaccurate results and optimizetiming closure
TimingVerification
Layout
CharacterizationBlock Model
TimingVerification/
TimingClosure
Place & RouteIntegration
Gate-levelVerification
Logic Synthesis
RTLVerification
RTLDesign
CharacterizationBlock Model
Layout
TimingVerification
Embedded Memory Design
CharacterizationBlock Model
Hard IPDesign
CharacterizationBlock Model
Layout
Timing/PowerVerification
Cell LibraryDesign
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In-Circuit Characterization Engine
Timing ModelGeneration
Automatic Circuit PartitioningCircuit Functional ExtractionAutomatic Vector GenerationUltra-Fast / Accurate Spice
FunctionalModelGeneration
Static TimingAnalysis
Power Characterization
Tool Performance:Fastest CharacterizationIncremental Analysis
Engineering Performance:•Automation•Ease of use
Design Performance:•Highest accuracy•Complete modeling
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Simucad Cell and Core Characterization Flows
AccuCellTimingPowerFunction
Timing
TimingPowerFunction
Functional Extraction
Vector Generation
Dynamic Simulation
ModelGeneration
Block/CorePartitioning
CharacterizationStatic
Timing AnalysisModel
Generation
ModelGeneration
Cell
Block/Core
AccuCore
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Scaleable Characterization Solution
Simucad’s characterization technology scales-up fromstandard cells to custom blocks to IP cores for use inFull-Chip STA
Full-Chip Environment
Timing Models.lib (all paths).lib (compressed).lib (black box).tlfSimucad format
Functional ModelsVerilog (gate level)Simucad format
Power Models.lib (standard cell)Simucad format
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Digital Circuit Verification Methods
ß Non-Hierarchical True SPICE Simulationß Highest accuracy, but with limited capacity, too slow and large manual vector
generation effort and will not achieve 100% coverage
ß Gate Level Simulation with SDF Back Annotationß Requires expensive dedicated emulation/acceleration hardware to simulate in
reasonable timeframes
ß Requires large manual vector generation effort and will not achieve 100% coverage
ß Requires detailed exhaustive library characterization effort
ß RTL Simulation with Formal Verification and Static Timing Analysis (STA)ß Fast functional verification with near 100% coverage
ß Dependent on some manual manual vector generation and has reduced timingaccuracy for advanced designs and advanced processes
ß Limitations in design style for high performance (dynamic logic, asynchronous)
ß Requires detailed exhaustive library characterization effort
ß Switch Level/Fast SPICE Simulationß Requires large manual vector generation effort and will not achieve 100% coverage
ß Adequate capacity but reduced accuracy
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Static Timing Analysis (STA)
ß Static Timing Analysis is a method of computing the expectedtiming of a digital circuit without requiring simulation.ß In a synchronous digital system, data is supposed to move in lockstep,
advancing one stage on each tick of the clock signal. This is enforced bysynchronizing elements such as flip-flops or latches, which copy theirinput to their output when instructed to do so by the clock. On first order,only two kinds of timing errors are possible in such a system:ß A hold time violation, when a signal arrives too early, and advances one clock
cycle before it should
ß A setup time violation, when a signal arrives too late, and misses the timewhen it should advance.
ß The time when a signal arrives can vary due to many reasons - the inputdata may vary, the circuit may perform different operations, thetemperature and voltage may change, and there are lot-to-lot, wafer-to-wafer and die-to-die manufacturing differences. The main goal of statictiming analysis is to verify that despite these possible variations, allsignals will arrive neither too early nor too late, and hence proper circuitoperation can be assured.
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In-Circuit Static Timing Analysis
ß Limitations of Traditional Gate Level Cell Library-based STAß Long characterization time
ß ALL possible cells must be characterized under ALL possible output loads andALL possible input slew conditions
ß Factor of N accuracy increase requires N2 simulation time increase
ß Accuracy lossesß Table interpolation errors
ß Real-world non-linear effects NOT modeled (PWL vs. actual stimulus, MillerEffects)
ß Elmore RC delay model limitations
ß Ignores actual chip routing dependent RC effects
ß Ignores Well Proximity Effects (WPE)
ß Ignores chip level IR drop effects
ß Benefits of In-Circuit Block Level Characterization and STAß Uses actual circuit loads, actual circuit slews and actual circuit RCs for both signal and
supplies
ß Rapid and accurate automated characterization with ALL in-circuit effects
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Definitions of Key STA Terminology
ß The critical path is defined as the path between an input and an output with themaximum delay. Once the circuit timing has been computed by one of techniquesbelow, the critical path can easily found by using a traceback method.
ß The arrival time of a signal is the time elapsed for a signal to arrive at a certainpoint. The reference, or time 0.0, is often taken as the arrival time of a clock signal.To calculate the arrival time, delay calculation of all the component of the path willbe required. Arrival times, and indeed almost all times in timing analysis, arenormally kept as a pair of values - the earliest possible time at which a signal canchange, and the latest
ß Another useful concept is required time. This is the latest time at which a signalcan arrive without making the clock cycle longer than desired. The computation ofthe required time proceeds as follows. At each primary output, the required timesfor rise/fall are set according to the specifications provided to the circuit. Next, abackward topological traversal is carried out, processing each gate when therequired times at all of its fanouts are known
ß The slack associated with each connection is the difference between the requiredtime and the arrival time. A positive slack s at a node implies that the arrival timeat that node may be increased by s without affecting the overall delay of the circuit.Conversely, negative slack implies that a path is too slow, and must be sped up ifthe whole circuit is to work at the desired speed
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AccuCore Static Timing Analyzer (STA)
ß AccuCore Static Timing Analyzer (STA) is a hierarchical gate levelanalyzer with full chip capabilities
ß It handles both sequential and combinational devices and can beused either as a standalone analyzer or as part of a unifiedcharacterization flow
ß In a standalone flow, STA operates independently ofcharacterization reading both a Verilog netlist and multiple timinglibraries in either the Simucad or Synopsys Liberty formats
ß It can also read interconnect parasitic data in SPF or SDF formatsWhen used in a unified flow, the process includes characterizationof the partitioned cells, or Design Clusters (DCs), creation of aVerilog interconnect netlist, and Simucad and/or Liberty formattedtiming libraries that eventually feed back into STA
ß Both flows enable full chip analysis of custom and ASIC blocks ina single run
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AccuCore Block Level STA Capabilities
ß Path Tracingß Finds the longest and shortest paths through the design
ß Traces critical and subcritical paths separately
ß Uses options to direct and limit search paths to areas of interest
ß Uses element function to propagate constants
ß Contains elaborate path-blocking capabilities
ß Accommodates clock propagation
ß Timing verificationß Verifies timing of flip-flops, latches, domino logic, dynamic elements,
muxes, and tristate elements;
ß Analyzes gated clocks and designs with clocks of varying frequencies;
ß Performs data-to-data timing checks for arbitrary nets in the design;
ß Accommodates multicycle paths
ß Performs customized timing checks for gated clocks and sequentialelements;
ß Back annotates interconnect parasitics’ information using SPF and SDFformats
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AccuCore Block Level STA Capabilities
ß Reportingß Reports longest and shortest pathsß Includes clock paths and data paths in timing check reportsß Reports path-based net-slack and gate pin slackß Provides data on the worst arrival and required time for both the net and
gate pinsß Reports the worst falling and rising arrival time on the net
ß Delay calculationß Supports conditional delaysß Supports scalar, one-dimensional and 2-dimensional tables of slope and
delay valuesß Supports max and min delay values with different vectors from the
Simucad library
ß SPICE deck generationß Generates SPICE deck of critical pathsß Generates SPICE deck of a clock tree
ß Modelingß Generates multiple models of the analyzed design
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AccuCore Full-Chip Level STA Capabilities
ß STAß Reads hierarchical Verilog netlist
ß Reads multiple libraries in the Simucad and standard industry synthesisformats
ß Back-annotates interconnect parasitics information using transistor orgate level SPF and SDF formats
ß Considers black box and compressed models
ß Enables constraint management
ß Modelingß Generates black box timing model
ß Generates compressed models, hiding details of the combinational paths
ß Generates interface compressed model to enable gate level SPF backannotation at the full chip level
ß Propagates slope tables during compressed model generation
ß Generates interface models with a detailed view of interface logic
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AccuCore Full-Chip Level STA Capabilities
ß Block constraint generation and slack allocationß Generates external timing and load gate pin or net based constraints for
hierarchical blocks from full chip timing analysis
ß Performs driver-receiver slack allocation based on user directives
ß Clock skew analysisß Allows the user to specify uncertainty, ie a skew relationship between
clock nets
ß Uses clock skew to find timing violations
ß Debugging capabilitiesß Provides complete information about clock propagation and clock
waveforms
ß Provides netlist, library, and analysis verification commands
ß Application Program Interface (API)ß Enables access to STA databases through TCL functions
ß Allows for the creation of customized reports
ß Allows for the creation of timing models in user-defined formats
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Using STA in a Standalone Flow
ß STEP 1: Creation of the Configuration Fileß Create configuration file
ß STEP 2: Creation of a TCL Scriptß Call the configuration file with sta_read_cfgß Library Verification – verify timing accuracy of library of cells
ß Verify connectivity between Verilog Netlist and Cell Library withsta_verify_netlist
ß Commands to find critical paths and verify critical and subcritical setup and holdtiming checks
ß Validate the script with verify_checks and report_checks
ß STEP 3: Clock Verificationß Clock propagation verification with find_paths, print_clock_waveforms
and report_warnings -all
ß STEP 4: Analysisß Limit analysis to specific nets, analyze false paths and subcritical nets
ß STEP 5: Evaluation of Resultsß Generate statistics and verify with SPICE using print_spice_paths
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STA in a Unified Flow
ß Characterization process is included for all of the gates anddesign clusters (DCs) being analyzed
ß More accurate because input slew and output loads areactual values—not interpolated tables
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Using STA in a Unified Flow
ß STEP 1: Creation of the Configuration Fileß Create configuration file with commands to characterize the circuit using in_file,
lib_cmd, do_sta, clock_time, input_time, output_timeß Validate the configuration file with sta_read_cfg
ß STEP 2: Creation of a TCL Scriptß Commands to find critical paths and verify critical and subcritical setup and hold
timing check with gen_model file.cfg added to initialize characterization
ß STEP 3: Running AccuCore with STAß Include gen_model file.cfg to analyze the block, partition the circuit into
design clusters, characterize them, and create the library
ß STEP 4: Evaluation of Preliminary STA Resultsß Analyze default report and run additional reports by adding commands to the TCL
file and .cfg file
ß STEP 5: Examining the User-requested Reportsß Use verify_checks to evaluate timing constraints on latch inputs and primary
outputs
ß Note that a negative margin indicates a violation
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Outline for Basic STA Operations (1)
ß Basic STA Operationsß Path Search
ß Controlling Path Search
ß Path Topology
ß Critical vs. Subcritical vs Latch-to-Latch Paths
ß Synchronizers and Transparency
ß Path Cycle Rules and Transparency
ß Default Synchronizer Rules
ß Latch Groups
ß Combinational Loops
ß Timing Constraint Verification
ß Timing Constraints and Clock Domains
ß Timing Constraints and Path Cycle Rules
ß Path Cycle Rules and Clock Uncertainty
ß Output/Bidir Assertions
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Outline for Basic STA Operations (2)
ß Basic STA Operationsß Checks for Latches and Flip-flops
ß Gated Clock Checks
ß Data-to-Data Checks
ß Tristate Bus Checks
ß Latch Loop Constraints
ß Common Skew Removal
ß STA Reports
ß SPICE Deck Generation
ß STA Timing Models
ß Block Constraint Generation
ß Slack Allocation
ß Interconnect Back Annotation
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Path Search
ß Ability to determine arrival time and the required time of all netsand use the information to prune the search space
ß Ability to locate all paths that contribute to a timing violationthereby avoiding the "onion peeling“ problem when implementinga fix
ß Full modeling of transparency for latches and other synchronizertypes
ß Ability to handle domino gates in combination with AccuCorecharacterization
ß Ability to manually control searches through blocking, constantpropagation, and cycle specifications
ß The two primary commands used with path search are:ß find_paths - For path-only searches with the results sorted according
to path endtime or path lengthß verify_checks - For determining the errors/margins of timing
constraints and the corresponding clock and data paths The results aresorted according to error/margin value
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Controlling Path Search
ß Blockingß Path Blocking - Blocks paths identified by their
start nodes, end nodes, and optionally thru nodes
ß Net Blocking - Blocks paths that pass through anet specified with the optionpath_block -thru_node
ß Arc Blocking - Blocks all paths that pass throughspecified input and output nodes of a gate
ß Bidirect Feedback Pathsß Inclusion of these paths is controlled with the
bidir_block command, but by default, they areexcluded In either case, there is no impact topaths through any internal bidirect drivers thatmay be contained in the circuit
ß Constant Propagation/Conditional Delayß Specify constant 0 or 1 value on selected nets
ß STA will propagate constants throughcombinatorial gates that can select amongmultiple delay values
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Path Topology
ß Paths always start from one of theprimary clocks or data inputs asdeclared in the configuration file
ß Design is assumed synchronous sotiming of internal events is relatedto change in a primary
ß Slope propagation begins at aprimary clock or data
ß Example cfg file for circuit at left:clocks main ph1 ph2clock_time ph1 rise_time=0 fall_time=1 period=2clock_time ph2 rise_time=1 fall_time=0 period=2inputs d1input_time d1 ph1 r rise_time=0 fall_time=0outputs outoutput_time out ph2 r setup_time=0 hold_time=0
ß Path search can be direct orindirect with –thru_mode option
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Critical vs Subcritical vs Latch-to-Latch Paths
ß Critical path refers to the longest (setup) orshortest (hold) path for a specific endpoint
ß Subcritical path is any non-critical path to anendpoint
ß Latch-to-latch paths refers to a subset of thesubcritical paths to endpoints which differfrom each other in the preceding latch of thepath, or in the primary input if there is nopreceding latch Each path of the subset isthe worst-case path from its preceding latchor primary input
ß At left, if the 9.0ps path is the critical path tolatch L4, then the latch-to-latch paths to L4would also include the 8.5ps and 8.8pspaths The complete set of subcritical pathsto L4 would also include the 7.0ps path Ifthe cycle time is 8ps, then not only thecritical path, but also the 8.5ps and 8.8pspaths must be found and corrected
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Critical vs Subcritical vs Latch-to-Latch Paths
ß Critical and subcritical path searches are useful for differentpurposes and, for efficiency, STA uses different algorithmsfor each of them
ß Modes for the path search commands:ß -critical(default mode)ß -subcriticalß -latch_to_latch
ß A critical path search uses thecalculation of arrival timewindows to prune the search
ß A -subcritical path searchuses the calculation of net slacksto prune the search and is bestfor exploring timing problems
Critical Path Search using Arrival Time Windows
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Subcritical and Latch-to-latch Path Search
ß A subcritical path search is also needed when thepath search must be forced to go through specifiednets using the -thru_node option of theverify_checks or find_paths commands
ß The latch-to-latch path mode can be thought of asintermediate between a critical path search and afull subcritical path search.
ß Subcritical searches tend to find large numbers ofpaths with the same sending and receiving latches,so it may not give broad coverage of the circuitwithin reasonable parameters for memory andruntime
ß The latch-to-latch mode can cover all latch pairsand provide more information than the criticalsearch without the detail of a full subcritical
ß Another difference between the path modes is inthe pruning of subcritical paths at transparentlatches
ß In critical and latch-to-latch mode, any subcriticalpaths will be pruned out at a transparent latch
ß In subcritical mode, however, there is no pruning ofvalid paths at transparent synchronizers
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Synchronizers and Transparency
ß Except for the purely combinational case, STAanalyzes a circuit as a collection of synchronizerscontrolled by the clocks defined in the configurationfile and connected by blocks of combinational logic
ß Synchronizers are the gates where signals mayhave to wait for a clock and can be latches, flip-flops, or domino gates
ß In addition, tristate-able gates and clocked muxesare treated as synchronizers if they werecharacterized by Accucore and if they have anunambiguous clock input
ß But, if there is no clock input whatsoever, thesynchronizers are treated as combinational gates
ß With the exception of flip-flops, synchronizers aretransparent when their clock is active
ß As a result, the latest output arrival time may bedetermined either by the latest data input arrivaltime or by the latest clock enable time as shown inthe figure to the left
ß In the case where data input is later than the clockenable, the terms “timing borrowing” or “flow thru”are sometimes applied
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Synchronizers and Transparency
ß For both critical and subcritical paths, pathsearch works through transparentsynchronizers
ß Transparency is checked by comparing thearrival times of the data inputs and the clockenable The process also takes into accountthe cycle rules between sending andreceiving synchronizers
ß There are two methods for determining theearliest synchronizer output time when thedata is later than the clock:ß In conservative mode, the earliest output time
is determined by the earliest clock enabletime only This ensures that any transienteffects from initialization are included
ß In non-conservative mode, the earliest outputtime is determined by the later of the earliestclock enable and the earliest data inputarrival time as shown at left An example ofhow this might be used is in the analysis of apipeline circuit in its steady state
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Path Cycle Rules and Transparency
ß AccuCore STA needs to know theintended source and destinationclock edge times for any pair ofsynchronizers
ß Based just on the clocksspecifications in the configurationfile, the edge times are onlydefined up to some multiple of theclock period as shown in theCycle Rules figure at left
ß As a result, it is necessary tomake default assumptions andprovide a way to manuallyoverride them
ß The manual overrides are oftenreferred to as multi-cycle pathconstraints
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Cycle Rules and path_cycle Command
ß The default clocking assumptions are changed with thepath_cycle command that comes in 3 types:ß path_cycle -sync <path_src_spec> <path_dest_spec> -cycle <value><R|L>ß path_cycle -setup <path_src_spec> <path_dest_spec> -cycle <value><R|L>ß path_cycle -hold <path_src_spec> <path_dest_spec> -cycle <value><R|L>
ß The -cycle value determines the number of cycles between the clock edges interms of an interval
ß The R or L suffix indicates whether the interval includes equality on the right or leftend
ß Insertion delays are not included when comparing clock edge times
ß When the source is a primary input/bidir, cycle rules are applied as if the input werecoming from a latch that is enabled by the edge specified with the commandinput_time in the configuration file
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Default Synchronizer Rules - Latch-to-LatchPairs
ß Since a latch is actually a genericsynchronizer, the rule for latch-to-latch pairs applies to anysynchronizer, with the exceptionof domino gates
ß It says that the nominal time of theenable edge at the destinationlatch can be the same as thenominal time of the enable edgeof the sending latch
ß It can also be later, but not awhole cycle later
ß This corresponds to the usualways that latches are clocked:data is passed between twophases that are less than a cycleapart, and in some cases thephases are the same as shown atleft
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Default Synchronizer Rules - Latch Groups
ß Path searching through transparentsynchronizers becomes more complexwhen there is sequential looping in thecircuit
ß To address this, the search is sub-dividedinto latch groups, a set of synchronizergates connected by sequential feedbackpaths
ß This means there is a topological path fromthe output of any synchronizer in the groupto the input of any other synchronizer andthat the path passes through combinationalblocks and possibly other synchronizers inthe group
ß For example, a latch group mightcorrespond to a state machine constructedusing latches and a two-phase clock
ß Synchronizers that are not in any sequentialfeedback loop are in a latch group bythemselves. This is always the case for flip-flops
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Latch Group Errors - Latch Loop Violation
ß When data passestransparently through alllatches of a loop, therequirement for synchronousoperation is violated
ß More specifically, the datashould have to wait for theclock in at least one latch ofany loop, but if the total delayexceeds the sum of the clockphases around the loop, anerror occurs
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Latch Group Errors - Latch Depth Violation andLatch Output Clipping
ß Latch Depth Violationß This error occurs when data passes transparently through more latches
than is allowed. The default value is 10, but this can be overridden withthe sta_set_max_depth command
ß Latch Output Clippingß This error results if data arrives at any latch of a group after the clock
disable edge
ß Depending on the options used with the path_search command, theerrors can be handled in one of two ways:ß By disabling the diagnostics with the no_latch_group_diagnostics
option, which is also the default; orß By enabling diagnostics with the latch_group_diagnostics option.
ß If the diagnostics are disabled, a warning is generated and all the data-to-output arcs of all the synchronizers in the group are made non-transparent
ß Although the analysis of the group is completed, no flow-through pathsare included for the synchronizers in the group. This option is moreefficient and is very useful for the initial run of a circuit.
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Combinational Loops
ß When STA finds a combinational loop, it breaks it by arbitrarily selectingone cell arc along the loop and blocking it
ß All paths through the blocked arc are then excluded
ß If a default break point would result in missing an important path, thebreak point can be moved to a different arc of the loop by blocking thedesired arc with the arc_block command. (Loop breaks, however,cannot be changed using the path_block command)
ß A list of the loop paths and their break points can be obtained using thereport_warnings -comb_loops command
ß Combinational loops often occur in interconnected groups called stronglyconnected components, or SCC’s
ß These are analogous to the latch groups discussed earlier, but arecomposed of just combinational gates
ß For SCC’s it can be helpful to know the whole structure and not just theindividual loops that are broken
ß The report_warnings -comb_sccs command shows all the gates,nets, inputs, and outputs of each SCC found
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Timing Constraint Verification
ß A timing constraint is a restriction on the minimum ormaximum allowed time between two signal edges
ß AccuCore STA can verify these types of timing constraints:ß Output/Bidir assertionsß Latch/flip-flop checksß Domino gate checksß Gated clock checksß Data-to-data checksß Tristate bus checksß Latch loop constraints
ß Timing constraints that are explicitly defined, either in thelibrary or by configuration commands, are verified using theverify_checks command
ß This will determine the error/margin value as well as thepaths for each check. The checks will be sorted accordingto the error/margin value
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Timing Constraints and Clock Domains
ß In STA, the term clock domain refers to a set of clocks thatare related in frequency and phase
ß A clock domain is defined by a clocks command in theconfiguration file. (In STA, complimentary domains like“main” and “!main” are combined as a single domain.)
ß STA carries out the analysis of each domain independently
ß STA does not consider synchronization or timingchecks between different domains. Data launched by aclock in one domain will not pass through a synchronizerunder control of a clock in a different domain, or have timingchecks done against data controlled by a clock in a differentdomain
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Timing Constraints and Path Cycle Rules
ß Clock cycle calculations are controlled by the path_cycle commandwith setup and hold having the following form:ß path_cycle -setup <path_src_spec> <path_dest_spec> -cycle <value><R|L>ß path_cycle -hold <path_src_spec> <path_dest_spec> -cycle <value><R|L>
ß There is a set of default setup/hold rules, which in most cases can beselectively overridden by adding path_cycle commands to theconfiguration file
ß The setup and hold rules operate independently of each other and of thesynchronization rules discussed earlier
ß When performing a setup or hold check, STA considers the source anddestination synchronizers and looks for a rule that matches thesynchronizer pair. If a match is found, the cycle rule value determines thenumber of clock cycles to assume between source clock enable edge andthe destination clock edge specified by the check. If no matching rule isfound, the check is omitted
ß The default rules are all based on a “less than or equal to one cycle”assumption for the time between source and destination clock edges
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Path Cycle Rules and Clock Uncertainty
ß If the reference clock edge times inthe configuration file have a min-maxuncertainty range, then it is the rangesthat are shifted by a multiple of theperiod to satisfy the cycle value of apath_cycle rule
ß When comparing two ranges, theminimum of one is compared with themaximum of the other; equality meansthat they overlap
ß When data is passed between clocksof different frequencies, but in thesame clock domain, there can bemore than one source-destinationclock edge pair to consider whenverifying constraints to ensure that theworst case is found
ß The possible edge pairs are stilldetermined by applying the default oruser-specified path_cycle rules, butthe clock period used with the ruledepends on the rule type
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Cycle Rule and Multi-frequency Clocks
ß For setup and sync rules, thedefault is the destination clockperiod, but for hold rules, it isthe source clock period. Thedefaults can be overriddenwith the –use_src_periodand –use_dest_periodoptions of the path_cyclecommand
ß Figure at left shows examplesof the edge pairs that would bechecked for rules having fourdifferent combinations ofedges, cycle values, andselected clock periods
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Output/Bidir Assertions
ß Output/bidir assertions are constraints imposed by theexternal environment. They are defined in the configurationfile by the output_time command
ß When checking output assertions, cycle rules are applied asif the output signal were being latched by the same clockedge as specified with the output_time command
ß In the example below, the out1 signal is treated as if it wereconnected to a latch that opens on the falling edge of ph1and closes on the rising edge
Example:clocks main ph1clock_time ph1 rise_time=0 fall_time=1 period=2outputs out1output_time out1 ph1 r setup_time=0.2 hold_time=0.1
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Checks for Latches and Flip-flops
ß The checks for latches and flip-flops include setup, hold, recovery, removal, skewand minimum pulse width constraints
ß In Simucad-formatted libraries the checks are defined by cons_arc statements. ForACCUCORE-generated libraries, the setup and hold values are determined bycharacterization
ß The default cycle rules for the setup and hold checks are:ß path_cycle -setup-src_local_edge latch_enable \
-dest_local_edge latch_disable -cycle 1Rß path_cycle -hold -src_local_edge latch_enable \
-dest_local_edge latch_disable -cycle 0R
ß These rules will match any latch or flip-flop source and destination. For a flip-flop,the latch_enable edge type and the latch_disable edge type are bothequivalent to the active clock edge of the flop
ß The first rule says that the nominal time of the clock edge for setup at thedestination latch is later than the nominal time of the enable edge of the sendinglatch, but not more than one cycle later. The destination edge is assumed to belater, rather than equal, since equality would imply a normally unintended racecondition, and also to handle the usual flop-to-flop timing case
ß The second rule says that the nominal time of the hold clock edge at thedestination latch may be equal to the nominal time of the enable edge of thesending latch, or it may be earlier by less than one cycle. Note that the -setuprule also applies to gated clock setup, tristate setup, and recovery checks. The -hold rule also applies to gated clock hold, tristate hold and removal checks
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Checks for Latches and Flip-flops
ß The example at left shows anexample of modifying thepath_cycle rules for a two-cycle path between twolatches
ß It assumes that hold checksshould be done against thesame edges as those forsingle-cycle paths
ß Note that the hold rule is thesame as the default and so itcould be omitted
ß “B” is the default of the threeexamples at left
A
B
C
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Checks for Latches and Flip-flops
ß At left is an example of modifyingthe path_cycle rules for a two-cycle path between two latches
ß It assumes that hold checksshould be done against the sameedges as those for single-cyclepaths. Note that the hold rule isthe same as the default and so itcould be omitted
ß For minimum pulse width checks,the default cycle rule assumesthat the signal edges come fromconsecutive, or the nearestpossible source, clock edges
ß This rule cannot be changed
ß “B” is the default of the threeexamples at left
A
B
C
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Gated Clock Checks
ß Gated clock checks areconstraints to ensure the stabilityof clock gating signals during theclock transition time
ß Gated clock checks can be addedby STA, the user, or be defined inthe library
ß By default, STA will assume thatclock gating is intended at anycombinational gate that has oneor more clock inputs, one or moredata inputs, and the booleanfunction of the gate is one of AND,OR, NAND or NOR
ß The verify_checks commandwith the options-gated_clock_setup and-gated_clock_hold can beused to selectively verify thesechecks
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Common Skew Removal
ß Common skew occurs when thedata and clock paths of a timingconstraint have shared gates andthe shared gates have a delayuncertainty or min/max range
ß By default, STA will use the maxdelay values in the long path andthe min delays in the short path,resulting in an overly pessimisticvalue for the margin
ß The resolve_common_skewoption of the verify_checkscommand will detect commonskew and adjust the margins toeliminate it
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STA Reports
ß AccuCore STA reports enable designers to:ß Verify timing check violations for clock controlled elements and
primary outputs
ß Analyze path lengths and signal arrival times
ß Perform net bottleneck analysis based on the net slacks
ß Create a net timing window report that can be used to further tunetiming by introducing a noise (x-coupling) factor to the analysis
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STA Report report_checks
ß The report_checkscommand is based ontiming checks performedby the verify_checkscommand
ß The report is sorted inorder of increasingmargin, or slack
ß Two paths are reportedfor every timing checkß The data path from the
clock/primary input to thepoint where the timingcheck is performed
ß The clock path for theclock that is used in thetiming check
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STA Report report_checks
ß Using report_checks, designers can see how manysetup and hold violations there are as well as their severityß The first run usually includes just the critical checks using only the
worst timing checks for every timing check instance
ß This report is preferred when checking the overall timing of thecircuit
ß When exploring specific problems, the ability to viewmultiple timing checks for the same timing check instancemay be desiredß Such a report can be generated with theverify_checkscommand in a special subcritical mode
ß The path format in the report can be customized using thesta_path_format command
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STA Report report_paths
ß The data for report_paths is based on path delays is createdusing the find_paths command
ß The report is sorted by the path length and can be customizedwith the sta_path_format command
ß The find_paths command has two modes:ß Critical when only critical paths are reported (default)
ß Subcritical that includes critical and subcritical paths
ß The critical mode refers to the path with the worst-case lengthor end time for a given end point and edge (rise or fall)
ß If the critical path for a given end point and edge is not unique,then a critical-only report will include one path, chosenarbitrarily; and the other paths will be contained in thesubcritical report
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STA Report report_paths
ß The critical mode isgenerally preferred forchecking the overallcircuit timing, whilesub-critical is usefulwhen exploring specifictiming problems
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STA Report report_net_slacks
ß The AccuCore STA slack reports show you how to make aminimum number of circuit fixes that will cover a maximumnumber of timing problems
ß The report_net_slacks calculates the worst slack for all nets
ß The slack is calculated separately for rising and falling signaledges and for different clock domains as a difference of worstrequired and worst arrival times at the given net for theappropriate edge
ß The report is sorted by the net slack
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STA Report report_path_slacks
ß The report_path_slacks is based on the results of thepreceding verify_checks, can be formatted withsta_slack_format must be run in the subcritical mode
ß This report lists the unique gates/nets that occurred in the paths,with worst-case output net slack, path count, worst-case delay,and worst-case slope
ß The slack limit and/or count limit can be optionally specified
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STA Report report_net_timing_window
ß report_net_timing_window aids in identifying net groups that may require additionalanalysis or that may need to be excluded from further tuning
ß The timing window is defined by the worst maximum arrival time and the best minimum arrivaltime relative to the edge of the reference clock for a stable (“0” or “1”) signal
ß Multiple timing windows are generated for different reference clocks. For the same referenceclock multiple timing windows are generated for different starting edges of the reference clock.The starting clock edge is the edge that generates the worst maximum arrival time
ß The best minimum arrival time is matched to the worst maximum arrival time as follows:ß If the element originating the best minimum arrival time is latch, flip-flop or a primary input, the matching worst
arrival time edge is the same clock edge that originates the minimum arrival time.
ß If the element originating the best minimum arrival time is domino, the matching worst arrival time edge is theopposite clock edge to the one that originates the minimum arrival time.
ß If the start and end clock edges are different types they are assumed to be in the same clockcycle
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SPICE Deck Generation
ß You can generate SPICE decks of critical paths to verifySTA results
ß print_spice_paths should follow the find_paths orverify_checks command
ß For the verify_checks command the SPICE deckincludes both a reference path and a data path. Pathnumbers are taken from the previous enumerated pathssummary or from the detailed path report generated by thepreceding find_paths or verify_checks command. Forexample:ß print_spice_paths 1-3 file=3.spi
ß AccuCore characterization generates the .out file withtransistor views of simulated partitions. This file should beincluded in the configuration file of the STA run using thein_txnetlist_name command. For example:ß in_txnetlist_name design.out
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Running SPICE on Generated Critical Pathsand Clock Trees
ß The SPICE deck contains a PWL waveform for each primary input withslope taken from either the input_time or the clock_timespecification in the configuration file
ß The technology and analysis parameters and output load are included ifspecified with the output_time command. Retain the MOSFET_TYPEcommand from the configuration file
ß Run SPICE and compare the delay of the path with the STA analysis
ß The -add_measure option can be added to the print_spice_pathscommand to automatically generate measure statements that assess thedelays from path input to path output and from gate inputs to gate outputs
ß The generated SPICE deck contains useful debugging information aboutpaths in the SPICE comments such as gate names, cell names, netnames, pin names, vectors, etc.
ß STA can generate the SPICE deck of a complete clock tree with theprint_clock_spice_deck command. It marks all gates traversedduring clock propagation, collects the termination load and thengenerates the clock tree SPICE deck
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STA Timing Models
ß The sta_create_model command generates an abstractrepresentation of the timing behavior of a block of circuitry
ß Models also allow for the distribution of designs betweendifferent design groups or even between differentcompanies where each design group can perform acomplete analysis of its share of the circuitry, generate atiming model and pass it to the design integration group thatwill perform a sign-off timing verification at the chip level
ß AccuCore STA supports:ß Non-transparent black box models
ß Compressed timing models
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Black Box Models
ß The non-transparent black box model contains only boundary pin information fromthe block
ß Inputs are modeled using setup and hold times to the first latch, outputs aremodeled as clock to output times, and combinational delays between primary inputpins and primary output pins are modeled as pin-to-pin delays
ß The black box model is environment independent meaning that all abstractedtiming arcs are independent of input arrival times and clocking conditions
ß The output of the black box generation is a single library file consisting of oneelement which can easily be integrated into the next level of timing analysis.
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Compressed Timing Models
ß AccuCore STA compresses all connected combinational gates of thedesign to a single gate without changing the sequential parts of the circuit
ß The output of the compressed model generation flow consists of two files:a new netlist file for the design and a new library file
ß The library file contains newly generated library cells for combinationalparts of the circuit as well as sequential elements from the original library
ß The model netlist contains newly generated combinational blocks withsequential elements and interface pins
ß Using these two files, the compressed model can be integrated as aseparate module into the full chip netlist for the final analysis
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Block Constraint Generation and SlackAllocation
ß External timing and load constraints may be created forhierarchical blocks defined by the commandsta_generate_constraints
ß All blocks must be defined as Verilog modules in the Verilognetlist
ß Timing constraints are created for every primary pin of thehierarchical block
ß The following constraints are created for different pins:ß Inputs/Inoutsß Worst rise/fall min/max slopes
ß Worst rise/fall max/min arrival times
ß Outputs/Inoutsß Worst rise/fall max/min setup times
ß Max/min rise/fall capacitances
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Block Constraint Generation
ß All constraints will be generated with respect to the edges orreference clocks
ß If more than one timing constraint is presented for the samemodule pin with respect to the same reference clock and thesame edge, they will be merged and only the worst one willbe recorded
ß Timing constraints for different clock edges of the samereference clock and for different reference clocks will berecorded separately
ß The output capacitance is the net capacitance for the netwithout parasitics
ß If parasitics are present on the net, the constraint cap will bethe worst ceff cap for the module output pin
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Block Constraint Generation Options
ß By default, AccuCore STA generates timing constraints tothe block boundary pins
ß Options to the sta_generate_constraints commandenable you to have constraints to the gate pins inside theinstance, rather than to the instance boundary pins
ß This option can be used when several drivers/receiversconnected through the distributed RC net on the full chiplevel and their constraints may be different based on theappropriate RC delay
ß STA then generates multiple timing constraints to the gatepins which allows better tuning of individual blocks
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Slack Allocation
ß Both drivers and receivers get 100% of slack by default butthe user can specify a slack allocation by using a specialoption of the sta_generate_constraints command
ß STA will first allocate the negative slacks based on the user-specified parameter
ß Each driver/receiver will be assigned the worst slack afteranalyzing all driver-receiver combinations based on theuser-defined criteria
ß After the negative slack is assigned, STA will allocatepositive slacks to only those drivers/receivers that don’t yethave any allocated slack
ß For positive slacks, the best case is assigned to eachdriver/receiver
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Interconnect Back Annotation
ß STA accepts information about resistive and capacitive interconnects ofthe gate level netlist in the form of Detailed Standard Parasitics Format(DSPF)
ß Usually AccuCore characterization accounts for all resistors andcapacitors at the block level
ß DSPF back annotation comes at a top level and represents interconnectsbetween blocks
ß DSPF can also represent interconnects at a gate level
ß Use the command in_spf_name to specify a DSPF file, orin_hier_spf_name to specify a hierarchical DSPF file
ß The DSPF parasitics file may contain RCs extracted either to the block orgate pins for ASIC blocks, or to the transistor pins for blockscharacterized by AccuCore
ß For the latter case, a special file will be generated containing transistor-to-gate mapping information that is used to match DSPF transistor nameswith a gate level netlist
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Interconnect Back Annotation
ß STA reads the DSPF file and models every net as a combination of driver-receiverpairs. The figure below shows the driver-receiver model for two inputs and oneoutputß The driver is the pi-network and represents the RC circuit as seen by the driving gate
ß The parameters of the pi-network are found by matching three moments of the RC circuit
ß The receiver is represented by Elmore delay RC, which is found by matching the first moment ofvoltage transfer function of the RC circuit
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Interconnect Back Annotation
ß STA calculates delays through interconnect in two stagesß First, the effective capacitance of the driver is calculatedß Second, the resulting waveform is used to calculate delay to the receiver
pinß The total delay is equal to the delay of the gate and the interconnect
delay
ß The effective capacitance is calculated by matching the chargeaccumulated in the pi-network to the charge accumulated at theeffective lumped capacitanceß The effective capacitance is a function of the input slope at the driving
point which in turn is a function of the effective capacitance andcalculated from the slope table representing the cell
ß The calculation uses an iterative algorithm which requires it to make aconsistent input slope at the RC input node with effective capacitance
ß At the second stage, the calculated waveform is applied at thereceiver and the delay of interconnect is calculated
ß The total delay is equal to the delay of the gate and theinterconnect delay
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Parasitic Reduction
ß The simplest form of interconnect information is a lumped capacitance of the netß In this case, net capacitance can be annotated using the command sta_node_capß Note that all occurrences of this command may be collected in one file that can be sourced from
the configuration file
ß STA will account for the net capacitance during delay calculation
ß An SDF file can be used to account for parasitics delayß In this case the file name is specified using the command in_sdf_nameß STA reads the SDF interconnect delays and includes them in the total delay to the receiver pin
of the next gate
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Input Libraries Merging Options
ß You can specify default (typical), max, or min libraries in either svcor synthesis formatsß The libraries are merged internally into the final library that is used for sta
analysis
ß The final library may be printed out using sta_print_lib command
ß The library merge is done using the following rules:ß First, the master library is chosen
ß If all three types of libraries are presented the default library is choosenas a master library
ß If no default library is presented, the max library becomes a default library
ß If multiple libraries of the same type are presented they are merged intoone library. The new library will consist of original library cells so thatevery cell appears in a new library no more than once
ß If multiple cells with the same name and the same type are presentedonly once, the arbitrary chosen cell is saved
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Input Libraries Merging Order
ß The order of the merge if all 3 types of libraries arepresented is:ß max library into the default library
ß min library into the default library
ß The libraries are merged cell by cell
ß The cell from the merged library will be merged into the masterlibrary only if the identical cell exists in the master library.Otherwise, the merged cell is ignored
ß Two cells are identical if they have the same name, the samenumber of pins, the same pin names and the same cell and pinattributes
ß When identical cells are found the timing information is mergedpin by pin into the master library
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Corners and STA
ß Behavior of an electronic circuit is often dependent on variousfactors in its environment like temperature or local voltagevariationsß In such a case either STA needs to be performed for more than one such
set of conditions, or STA must be prepared to work with a range ofpossible delays for each component, as opposed to a single value
ß If the design works at each extreme condition, then under the assumptionof monotonic behavior, the design is also qualified for all intermediatepoints.
ß The use of corners in static timing analysis has several limitationsß It may be overly optimistic, since it assumes perfect tracking - if one gate
is fast, all gates are assumed fast, or if the voltage is low for one gate, it'salso low for all others
ß Corners may also be overly pessimistic, for the worst case corner mayseldom occur
ß In an IC, for example, it may not be rare to have one metal layer at thethin or thick end of its allowed range, but it would be very rare for all 10layers to be at the same limit, since they are manufactured independently
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Conclusion
ß AccuCore Transistor and Gate Level Full-Chip STA with Automatic BlockCharacterization provides Static Timing Analysis (STA) of complexdesigns with mixed design styles. It gives designers the ability tocharacterize a multi-million transistor design with SmartSpice accuracyand perform block or full-chip static timing analysis
ß Key Benefitsß Complete Static Timing Analysis (STA) environment quickly identifies timing
bottlenecks leveraging state-dependent models
ß Automated False Path removal addresses bi-directional transistors
ß Easy setup enables mixing of custom and ASIC blocks in SoC environment
ß Automatically partitions multi-million transistor, flat or hierarchical design withparasitics into Design Clusters for accurate SPICE level characterization
ß Largest collection of calibrated SPICE models for CMOS and SOI, including BSIM3,BSIM3SOI, BSIM4, PSP, and HiSIM
ß Produces timing models for Cadence and Synopsys PrimeTime®
ß Generates fully-sensitized SPICE deck for critical paths and clock trees