a system design and build course on wearable computers
DESCRIPTION
A System Design And Build Course On Wearable Computers. Dan Siewiorek and Asim Smailagic Carnegie Mellon University MSE ‘01, Las Vegas, June 2001. Overview. Introduction Approach Electronic Design in a Multidisciplinary Project Design Methodology Power Measurements Evaluation - PowerPoint PPT PresentationTRANSCRIPT
Carnegie Mellon
A System Design And Build Course On Wearable Computers
Dan Siewiorek and Asim Smailagic
Carnegie Mellon University
MSE ‘01, Las Vegas, June 2001
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Overview
1. Introduction
2. Approach
3. Electronic Design in a Multidisciplinary Project
4. Design Methodology
5. Power Measurements
6. Evaluation
7. Conclusions
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Introduction
A System - Level design approach to the power and performance of CMU’s wearable computers dedicated to speech processing - the Speech Translator Smart Modules
Power consumption has to be considered in all phases of system design
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Introduction
We examine the impact of processor speed, memory size, and type of secondary storage on power consumption and performance
We see ahead a world of near-zero energy / weight / cost mobile systems
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Approach
Experimental framework includes a family of CMU wearable computers dedicated to speech processing - Smart Modules
They perform speech recognition, language translation, and speech synthesis
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Multidisciplinary Project
Five major factors in a portable electronic system include:
• Functionality
• User Interface
• Physical Form Factor
• Power
• Sensors
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Multidisciplinary Project
• Decisions made in one design discipline affect decisions in another discipline
• The impact can be measured if the cost of the design decision can be reduced to a common “currency”
• In mobile electronic systems that “currency” is power consumption
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Major Factors in Portable Electronic Systems and their
Relationship to the Design Disciplines
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Smart Module Architecture
The core of the smart module is the Cardio processor card, combining the processor and motherboard chips
The Cardio also supports two serial ports for communication between the modules and a VGA interface
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Smart Module Hardware Diagram
CARDIO
-Processor
-Memory
-Chipsets
KeyboardMouseVGA
PCMCIAHD
ESS 1888
IDE ISASerial
Ports
Communications
To other Modules
(For debugging only)
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Approach
The code was profiled and tuned
Profiling identified “hot spots” for HW and SW acceleration, and places to reduce computation and storage requirements
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Power Measurements
Power is consumed by
• Processor
• Memory
• Disk
• Sound Chip
• Serial Ports
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Power Measurements
The power and performance measurements were taken using a body of 10 English test sentences for the Speech Recognizer and Language Translator, and their 10 Croatian translations for the Speech Synthesizer
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Power Measurements
A power profile for the Smart Modules included:
• Idle Mode: processor is at nearly 0% usage
• Full On Mode: processor is at nearly 100% usage
Each state transition has an associated latency value
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Power Measurements
States for spinning disk drive:
• Power Down Mode: power to the disk drive is shut off - when the module is in Suspend Mode
• High Spin Mode: disk drive is being accessed
• Low Spin Mode: power-saving mode
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Power Measurements
State diagrams for both processor and disk were combined to produce a new model for power consumption
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New Model of Power Consumption Over Time
Power (W)
Time
Suspend
Idle & High Spin
Full on & High Spin
Idle & Low Spin
Full On & Low Spin
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Power Consumption Profile
Power consumption of the Speech Recognizer module over time, using the 586-based Cardio and a spinning disk drive, was measured
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Power Consumption of Speech Recognition Module Over Time
Suspend
Spin
Up
Full Spin Spin Down
Spin Up
Spin Down
Close TCP Link & Spin Up
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Performance Comparison
The metric for comparison is proportional to the processing power, and inversely proportional to the product of volume, weight and power consumption
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Name SpecInt Volume (in3) Weight ( lbs ) Power (watts) R (V*W*P) Log of Normalized
TI 6030 175.00 260.00 7.50 36.00 70200.00 0.00
TIA-P 55.00 88.00 3.00 6.50 1716.00 1.11
TIA-O 55.00 45.00 2.50 4.50 506.25 1.64
SR-SM 175.00 45.00 2.13 4.00 382.50 2.26
OPT-SM 175.00 33.00 1.50 4.00 198.00 2.55
Performance Values for Wearable Computers
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Composite Performance of Speech Recognition Wearable Computers
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 1 2 3 4 5 6
Evolution of Systems
Norm
Log
[p
erf
/(vol*
wt*
pow
er)
]
Normalized Performance
Goal: 2.8
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Spot: SA-1110 Based Wearable Computer
• New wearable computer as a research platform, including context aware computing
• Low power design• 233 MHz StrongARM 1110• 256 MB DRAM• Mobile, throttleable platform that can trade
performance for energy
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Conclusions
Results show that there are orders of magnitude improvement from one generation of wearable computers to the next
A system-level approach to power / performance optimization improved the metric by over a factor of 300 through the four generations, and over 400 through the five generations
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Conclusions
Peak demand by an application can often determine the battery life rather than average demand
Audio-centric interfaces exhibit high demand “spikes,” potentially causing significantly reduced battery life
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Summary
• The options for the design space included:– Two processor architectures (Intel 486,586)– Three different processor speeds– Two different main memory sizes– Two different secondary storage types
• The best configuration for performance is the 586/100/32 Flash, and the 486/75/16 Flash for power
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Power Consumption of Speech Recognition Module
• Our research indicates that the peak demand of an application can often determine the battery life rather than the average demand
• Audio-centric interfaces exhibit high demand spikes
• By filling in the valleys, it would be possible to cut the peak demand in half and thus significantly extend battery life