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A LOW POWER CMOS TRANSCEIVER DESIGN FOR MEDICAL IMPANT COMMUNICATION SERVICE Huseyin S Savci, Pin Ying, Zheng Wang and Prof. Numan S. Dogan North Carolina A&T State University An ultra low power CMOS transceiver has been designed for a usage in medical implant communication service devices. The FCC regulated MICS band which is 402- 405 MHz, requires ultra low power transceiver for medical implants. The following section gives a brief description of different sections of transceiver. The schematic and measurement results are included for each sub-block of the transceiver. There are three main section in this transceiver; Receiver, Transmitter and Frequency Synthesizer. 1. RECEIVER The architecture of Ultra Low Power CMOS MICS Homodyne Receiver is shown in Figure 1-1. The direct conversion architecture is selected for its lower power consumption. The communication system was designed to work with FSK modulation scheme. The receiver has LNA, Mixer, Pre-Amplifier, BB Filter, and Limiting Amplifier. The total voltage gain is more than 120 dB. This gain is high enough to allow limiting amplifier clip the amplitude of very low power incoming signals (-115 dBm) at VDD. The receiver has tunable bandwidth between 170 kHz and 250 kHz. The analog circuits at the downconverted path were designed to have lower flicker noise. The receiver uses DC-free modulation scheme which takes care the dc offset problem by ac coupling the signal between blocks. The overall power dissipation is around 4 mW. In order to have low power dissipation and moderate RF performance all of the transistors are biased in moderate inversion region where the device parameters are highly dependent on the process variations. Therefore the process corner analyses are carefully employed to ensure the proper operations of the circuits.

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A LOW POWER CMOS TRANSCEIVER DESIGN FOR MEDICAL

IMPANT COMMUNICATION SERVICE Huseyin S Savci, Pin Ying, Zheng Wang and Prof. Numan S. Dogan

North Carolina A&T State University

An ultra low power CMOS transceiver has been designed for a usage in medical

implant communication service devices. The FCC regulated MICS band which is 402-

405 MHz, requires ultra low power transceiver for medical implants. The following

section gives a brief description of different sections of transceiver. The schematic and

measurement results are included for each sub-block of the transceiver. There are three

main section in this transceiver; Receiver, Transmitter and Frequency Synthesizer.

1. RECEIVER

The architecture of Ultra Low Power CMOS MICS Homodyne Receiver is shown

in Figure 1-1. The direct conversion architecture is selected for its lower power

consumption. The communication system was designed to work with FSK modulation

scheme. The receiver has LNA, Mixer, Pre-Amplifier, BB Filter, and Limiting Amplifier.

The total voltage gain is more than 120 dB. This gain is high enough to allow

limiting amplifier clip the amplitude of very low power incoming signals (-115 dBm) at

VDD. The receiver has tunable bandwidth between 170 kHz and 250 kHz. The analog

circuits at the downconverted path were designed to have lower flicker noise. The

receiver uses DC-free modulation scheme which takes care the dc offset problem by ac

coupling the signal between blocks. The overall power dissipation is around 4 mW. In

order to have low power dissipation and moderate RF performance all of the transistors

are biased in moderate inversion region where the device parameters are highly

dependent on the process variations. Therefore the process corner analyses are carefully

employed to ensure the proper operations of the circuits.

Figure 1-1: Complete Receiver Architecture

Low Noise Amplifier

Figure 1-2 has a circuit topology that is commonly used in the design of CMOS

low noise amplifiers. This circuit has an inductive source degenerated input stage to

provide both input match and current gain at the resonant frequency. The cascode

transistor reduces reverse gain through the amplifier by mitigating the interaction

between the input tank and output tank which results increased stability of the circuit.

Furthermore, it reduces the Miller effect of Cgd of M1 by presenting a low impedance

node at the drain of M1. The output inductor Ld is designed to resonate at w0 with the

node capacitance at the drain node of the cascode transistor. In order to have ultra low

power consumption the transistors designed to on border of moderate inversion region.

The total power dissipation is about 830 µW. It has power gain of ~12dB and noise figure

of 1.3 dB.

Figure 1-2: Differential LNA

After all the measurements are performed the component and trace loss of the

PCB has been measured by removing the chip and soldering the semi-rigid coaxial

connectors. Then the board losses are de-embedded from the measured gain based on the

gain relation formula of cascaded two port networks and de-embedded from the noise

figure based on the friis formula. Figure 1-3 and Figure 1-4 shows the measured results of

LNA after de-embedding process.

Figure 1-3: Measured LNA Small Signal Parameters

Figure 1-4: Measured NF of LNA a) before & b) after; de-embedding the PCB and

Component Losses

Double Balanced Gilbert Mixer

A double balanced differential mixer has been designed to be used as direct

conversion mixer. The mixer has 7 dB conversion gain and consumes only 750 µW.

Figure 1-5 shows the schematic drawing of the mixer.

Figure 1-5: Double Balanced Gilbert Mixer

The mixer measurement is done with Tektronix Active Differential Probe at the

IF port. Figure 1-6 shows the down-converted output of the mixer for an RF signal at the

200 250 300 350 400 450 500 550 6004

6

8

10

12

14

16

18

20

22N

oise

Fig

ure

(dB

)

Frequency (MHz) 200 250 300 350 400 450 500 550 600

2

4

6

8

10

12

14

Noi

se F

igur

e (d

B)

Frequency (MHz)

input with -30dBm power level. The output is capacitively coupled to the probe. Due to

the high pass characterictic of such a coupling, the output reaches its normal value which

is -23 dBm after a while. The figure shows that the conversion gain of the mixer is 7 dB.

Figure 1-6 The IF output spectrum of Mixer for an input RF signal with -30 dBm power

Low Voltage High Phase Margin OTA

A low voltage, low current, two-stage OTA with a phase margin enhanced common-

mode feedback (CMFB) circuit has been designed to be used in the tunable channel select

filter. The schematic of OTA is shown in Figure 1-7. The input stage is designed to

satisfy the desired bandwidth and noise characteristics whereas the output stage is to

drive the resistive and capacitive loads. The input transistor pairs are chosen as wide as

possible to lower the flicker noise. To access body terminal of input nMOS devices,

triple-well transistors were used. The body terminals of these devices are biased with a

voltage of VDD/2. The resulting forward biased body-source lowers the VT and further

increases inversion level. The transistors operates near the weak-moderate inversion level

which increases input transconductance, gm, at lower drain current hence the lower power

dissipation. The miller compensation capacitors and resistors adjust the unity gain

frequency while increasing the phase margin.

Figure 1-7 Schematic of Operational Transconductance Amplifier

The common-mode feedback circuit designed in this work is composed of transistors

M1A-B-C-D, M2A-B and M3A-B. The CMFB circuit senses the DC outputs of OTA, compares

it with reference voltage VREF thru the mirrored current and generates an error voltage to

bias M3 and M4. The change in the bias point of M3 and M4 inversely affects the DC

output voltage of OTA. This closed loop continuously forces the output voltage to be

equal to the reference voltage. The CMFB loop has very high gain. The stability of this

loop is ensured by means of CC3 and RC3 which simply enhance the phase margin. The

common mode feedback circuit is designed to have accurate output balancing and stable

operation.

The simulated performance is summarized in Table 1-1. The gain and phase response of the amplifier are shown in Figure 1-8.

Table 1-1 Simulated performance parameters of OTA

Power Dissipation 86 µW Gain Bandwidth Product 17.25 MHz OpenLoop DC Gain 70 dB Input Noise 15.95 nV/√HzPhase Margin 52 ° CMFB Phase Margin 46 ° Unity Gain Frequency 20 MHz Dominant Pole Frequency 5.4 kHz

Figure 1-8 Gain and phase response of OTA

The individual measurement of OTA has not been performed. The performance of

the OTA can be indirectly estimated from the measurement of the filter.

Tunable Continuous-Time Low Pass Filter

A 5th order continuous time tunable elliptic low pass filter has been design for

channel selection of the receiver. The elliptic filter gives enough attenuation with high

selectivity in the stopband. The leap frog configuration is used as shown in Figure 1-9.

Figure 1-9: 5th Order Elliptic Low Pass Filter

100 101 102 103 104 105 106 107 108-60

-40

-20

0

20

40

60

80

Gai

n (d

B)

Frequency (Hz)100 101 102 103 104 105 106 107 108

-225

-180

-135

-90

-45

0

45

90

Ph

(d)

GainPhase

RL RL

RL RL RLRL

CL CL CLCL

RLRL

RL RL RLRLRLRL

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RL RL RLRLRLRL

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Vbias Vbias

VbiasVbias

VbiasVbias

VbiasVbias Vbias

RL

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Vout-

Vout+

Figure 1-10 shows the measured frequency response of the filter. The total power

consumption is around 480 µW. The filter has digitally assisted tuning range of 80 kHz

from 170 kHz to 250 kHz.

Figure 1-10: Measured Normalized Gain of Tunable Continuous-Time LPF

Limiting Amplifier

The final stage in the zero-IF receiver before ADC is limiting amplifier. Limiting

amplifiers are used when a circuit requires amplitude compression. They supply a good

protection for subsequent components by preventing input overdrive and removing the

amplitude modulation from frequency modulated signals. The limiting amplifier is

cascaded of simple differential amplifiers. The number of amplifier can be determined

based on the gain requirement. The amplifiers have high pass filter characteristics at the

input which eliminates the DC offset problem. Single stage of limiting amplifier is shown

in Figure 1-11.

Figure 1-11: Limiting Amplifier

Figure 1-12 shows the output waveform of whole receiver so the limiting

amplifier for a input of sinusoidal RF signal at 404.2MHz with -80 dBm power. The

peaking at falling edge and amplitude imbalance is due to the active calibration error of

differential active probe used to measure baseband signal.

Figure 1-12 Measured output waveform of the receiver for a sine RF signal at the input

20 25 30 35 40 45 50

-0.6

-0.4

-0.2

0

0.2

0.4

Time (µs)

Am

plitu

de (V

)

Figure 1-13 shows the die microphotograph of the MICS transceiver. The

different building-blocks highlighted.

Figure 1-13: Chip photo with sub-block representation

A single testboard has been designed for different measurement schemes. Figure

1-14 shows the photo of the testboard. An FR-4 substrate with 31 mil thickness has been

used. CPW structure is adopted for RF traces for its compact size.

Figure 1-14: Testboard for Receiver Section

2. TRANSMITTER Figure 2-1 shows the transmitter architecture. Compare to the reported MICS

architecture [1][2], this transmitter has both nonlinear transmitter path and linear

transmitter path. The low power operation is based on the nonlinear transmitter. For the

nonlinear transmitter, FSK has been chosen as the fundamental transmit modulation

scheme for it is the simplest nonlinear modulation that allows low current circuit design.

The linear transmitter allows much higher data rate with linear modulation schemes such

as 8 phase shift keying (8PSK). The data rate will be close to the three multiples of

channel spacing 300 KHz. The high speed of linear transmitter can be used when high

speed transmission such as image is needed. Same as nonlinear transmitter, relatively

high efficiency design is needed while ensuring the required linearity and output power.

Figure 2-1 Proposed Transmitter Architecture

Nonlinear Transmitter

The designed class E PA schematic is shown in Figure 2-2 and 2-3. L1 provide

DC feed. L2 and C1 provide serial resonance to the load R. C2 is the capacitor parallel to

the switching transistor. The ideal nonlinear model could be found in [3][4]. M1, M2 and

M3 M4 makes two inverters to buffer the FSK signal from VCO. M5 and M6 is the

switch for the class E power amplifier. At 400 MHz, the inductor values are too big to be

on chip so that L1,L2, and C1 have to be on board. The ideal value of inductor L1 and L2

is 4.7uH and 1.3 uH. However, commercially available inductors at such big value are

having very low self resonant frequency. Therefore, both L1 and L2 can only be 150 nH

the maximum. The SPICE model of the 150 nH inductors are shown in Figure 3.1.

Because SAW filter could have its impedance to be the same as the optimum load of for

1V, -2dBm PA, which is 100 ohm, the class E PA tank works as impedance matching as

well. M7 and M8 block is a process and supply sensor. The drain voltage is used as a

negative feedback voltage to bias the body of M6, in order to maintain constant output

level of nonlinear transmitter. M6 is a deep N-well device.

Figure 2-2 Nonlinear Transmitter Schematics Top Level

Figure 2-3 Nonlinear Transmitter Schematics

Linear Transmitter

Figure 2-4 Linear Transmitter Schematics –Top Level

Figure 2-5 Linear Transmitter Schematics -Modulator I Branch

Vee

Figure 2-6 Linear Transmitter Schematics -Push Pull Class-AB PA Figure 2-4, 2-5, and 2-6 are the linear transmitter schematics. Figure 2-4 is the top

level test setup and the no external component. Figure 2-5 is the I branches of modulator.

Figure 2-6 is the buffer, balun and class AB power stage.

Both I and Q branch has a double balanced mixer with differential input and

output. Here the tail inverter mixer is used for its more complete switching than Gilbert

Cell mixer in this low supply voltage case. The double balance is needed here to suppress

the LO to RF leakage. This proposed modulator architecture has potential for even lower

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Figure 2-9 Nonlinear Transmitter Output Performance

Table 2-1 Nonlinear Transmitter Summarized Measurement Results Measured Comments

Output Power -2 dBm As designed

Gain Variation +/-1.5dB for +/-10% supply voltage change

As designed Proved DBB techniques

Current Consumption 4.8 mA As designed 2nd Order Harmonics -30 dB As designed

Linear Transmitter

The linear transmitter measurement results are shown from Figure 2-10, 2-11 and

2-12. Figure 2-10 is the time domain waveform, but with long time duration to show the

modulated signal beating at 100 KHz. The marker in Figure 2-11 for the signal output

level reads -16 dBm which is 7dB lower as designed. This is due to the less optimization

in layout to minimize the parasitics for the transistors. When supply voltage varies from

0.9 V to 1.1 V, the output level changes by 3 dB. This proves the correct working DBB

compensation for linear transmitter as well. The current reads 6.2 mA at this time which

is also as designed. Figure 11 also shows the sideband level and LO leakage level. The

good sideband suppression proves I and Q branch are matched pretty well [5]. Most

importantly, Figure 11 shows very good linearity of the modulator for its diode loading

approach. The 3rd products are 30 dB below. The 2nd order harmonics of the nonlinear

transmitter is measured at 18 dB below as in Figure 12 and will be filtered. The linear

transmitter measurement results are summarized in Table 2-2.

Figure 2-10 Linear Transmitter Output Beat

Figure 2-11 Linear Transmitter Output Spectrum

Figure 2-12 Linear Transmitter Output Harmonics

Table 2-2 Linear Transmitter Summarized Measurement Results Measured Comments

Output Power -16 dBm Known issue due to less

optimized layout parasitics

Gain Variation +/-1.5dB for +/-10% supply voltage change

As designed Proved DBB techniques

Current Consumption 6.2 mA As designed

Linearity -30 dB As designed

Sideband Suppression -20 dB without calibration As designed

LO Leakage -15 dB without calibration As designed

2nd Order Harmonics -18 dB To be filtered

3. FREQUENCY SYNTHESIZER The frequency synthesizer is shown in Figure 3-1. It includes prescaler, type-II

Charge Pump Phase Lock Loop, and the VCO with DBB (Dynamic Body Biasing)

technique. A VCO without DBB technique will be a counterpart to be a comparison.

According to the specification of MICS (Medical Implant Communications Services),

and the frequency plan and scheme for the receiver and the transmitter, the comparison

frequency will be 100 kHz. The frequency range is defined by FCC, which is 402 MHz to

405 MHz. 10 channels will be assigned, therefore, each channel will have 300 KHz

channel spacing. Since the spacing consuming and peak Q value for this frequency range,

the VCO will oscillate at twice of the actual frequency, which is 804 MHz to 810 MHz.

And considering the nonlinearity tuning in VCO, the tuning frequency will be a little bit

more than twice wider, which becomes the 800 MHz to 814 MHz. Thus, the prescaler

should have the division ratio of 8000 or so. The schematic of the prescaler is shown in

the box in Figure 3-1.

Figure 3-1 The block diagram of the Frequency Synthesizer.

To select the frequency, P-Counter will have the division ratio of 2010. The

N/N+1 divider sets the N of 4. An S-Counter will set the selection of 60. Therefore, the

step frequency generated will be 100 KHz. The output signals of VCO will be divided by

two. It not only creates the center frequency in the range of 402 MHz to 405 MHz, but

also generates the quadrate signals for mixers both in receiver path and transmitter path.

So the quadrate signals will have the step of 50 kHz, which is suitable either for the FSK

balloon signals and MSK center frequency selection.

VCO with Dynamic Body Biasing (DBB)

The CMOS LC VCO design has significant potential for ultra-low-power

applications. Figure 3-2 shows the LC VCO design that employs the current reuse

technique. NMOS and PMOS transistors in Figure 3-2 form the cross-coupled pair that

generates the negative impedance. The current reuse technique yields the voltage control

oscillator operating at very low power consumption, low supply voltage. The VCO has a

superior phase noise performance and almost rail-to-rail output swings. However, this

VCO architecture has a drawback for practical implementation, namely the sensitivity of

drain current to process and supply voltage variations. Simulation results show the

current consumptions for different process corners and the ±10 percent supply voltage

variation. We observed that the current consumption is very sensitive to the process

variations namely slow-slow (SS) mode, nominal case (TT), and fast-fast (FF) mode.

Current consumption deviates more than twice for a 10% change in supply voltage.

PFDLP

Prescaler

Buffer

VCO @ 0.8 GHz

1/120 Divider

XTAL Ref. Osc. @12MHz

I & QTo Mixer

½ Divider

CPUp

Down

100KHz

Phase Lock Loop for MICS

fin = (NP + S) foutWhere N = 4, P = 2010,

and S = 00-60Prescaler

Divide by N / (N+1) P Counter

S Counter

fin fout

Reset

Channel Selection

Modulus Control

VCO with Dynamic Body Biasing

M1

gnd

P1

Vdd

R2 R1

C1

L1 L2

Sense and Feedback Circuits

R3

C3C2

External

Compared with the worst cases, the two extreme corners, such as left upper corner and

right lower corner, there is more than 20 times difference in the current (60 µA and 1.2

mA). The current is merely determined by the size (W/L ratio) of N- & P- MOS pair,

VDD, and the process parameters. There is nothing to restrict the current (i.e., tail current

source in diff. pairs).

Figure 3-2 CMOS LC VCO design with current reuse technique.

We employ the LC VCO design in Figure 3-1 that uses dynamic body biasing to

reduce the variations of drain current to process corners and supply voltage variations. A

small-value resistor R3 plays the role of current sensor. The sensed drain current is

converted to voltage and then will be amplified. The AC component in the signal will be

filtered out. The feedback circuit finally will produce a pair of DC voltages that are used

to bias the bodies of nMOS and pMOS transistors. The sense and feedback circuits are

formed by multi-stage amplifiers and low-pass filters. The sensed signal is relatively

small (few milli-volts) and has the oscillation components. Thus, the filter removes the

AC components. In order to control the body of the nMOS, M1 is implemented as a triple

well NFET. When the current in VCO core increases, the sensed voltage rises up initially.

Outputs of the negative feedback circuit would move up or down to shift the threshold

voltages of NMOS and PMOS to counteract the initial current increase in the VCO core.

There are limitations for these two bias voltages. Since the body-source junction becomes

forward biased for |VSB| > 0.6 V current is injected into the body terminal of the

MOSFET which is undesirable.

The simulation results for the proposed VCO with dynamic body biasing are

shown in Table 3-3. Compared to the results in Table 3-1, we observe that sensitivity of

the drain current to process and supply voltage variations are much reduced.

Figure 3-4 Test Board for Frequency Synthesizer

The transient response is shown in Figure 3-5.

Figure 3-5. The transient waveform of one of outputs at VCO.

Figure 3-6 center frequency of 937MHz for bits of 00.

Figure 3-7 center frequency of 948MHz for bits of 11.

The center frequency measured on one test board is 937MHz, which is 130MHz

or so higher than what the target is. The coarse tuning only brings 2MHz each step.

Figure 3-6 and 3-7 show the center frequency of 937MHz for bits of 00, the lowest

frequency and 944.8MHz for bits of 11, the highest frequency. Early when the VCO was

designed, such problem has already been existing. When the layout was extracted for

post-layout simulation, the switches options for the parasitics extraction were available. If

the different switches were selected, the center frequency of VCO could vary more than

120MHz. Although there are two switches were recommended, the other switches are

still not clearly described. And the simulation on the schematic also has more than tens of

MHz frequency difference. Since in the Medical Implant Communications Services, the

frequency range is narrow. The fine tuning should only cover the frequency plan and sort

of narrow guard band to avoid the nonlinearity of the varactors in the tuning range.

Therefore, 2-bit coarse tuning was applied to cover the center frequency shift due to

parasitics. But the same problem of the parasitics estimation on those capacitors happens

again. The center frequency is very sensitive to the exact values of LC tank and the

parasitics. Based on the performance of the silicon results, those values including LC

tank, coarse-tuning capacitors, and fine-tuning capacitors were all underestimated. That

results all values smaller in reality. So such large shift on the center frequency is

explainable. And why both coarse tuning range and fine tuning range are narrower is

understandable.

The phase noise measurement of VCO with Dynamic Body Biasing is also shown

in Figure 3-8. The phase noise at 1 MHz offset from 938.69 MHz shifted carrier

frequency is -112.5-dBc/Hz, which is a good phase noise performance for such low

power consumption level.

Figure 3-8 Phase noise performance for VCO with DBB

Table 3-1 shows what the current consumption for these two VCOs are. They are

so much different. It indicates that the VCO with DBB technology well controls the

variation of current consumption from power supply. The consumption is including some

needed for the package such as clamps, which burns more current than simulation

without package information. But its counterpart does not although it is burning the same

extra current. The VCO without DBB varies current consumption much just as what we

expected. When the power supply drops down to around 0.85V, the VCO with DBB

stops oscillation. It is what we expected too since the cross-coupled MOSFET pair

forming a cascode topology when both of them are on consuming at least 2VTH, which

they are added together to around 0.85V.

Table 3-1. Comparison of Current Consumption for two VCOs VCC 0.9V 1.0V 1.1V

VCO w/ DBB 802µA 854 µA 952µA VCO w/o DBB 1.57mA 3.97mA 6.07mA

Since we could not tune the center frequency to wanted band, we only could

measure the rest of the PLL blocks separately. The prescaler is a frequency divider with a

factor more than 8000. The performance of this block is good. Figure 3-9 shows the

frequency detected at the output “Fbk,” which indicates a frequency of 100 kHz exactly.

Changing the division ratio when changing the input frequency simultaneously, we got

the same performance. And as predicted, the duty cycle is 50 percent. The part of PFD

and charge pump has not done yet since a two tune function generator is needed to have

two correlated signals.

Figure 3-9 The output frequency at test node of “Fbk.”

ACKNOWLEDGEMENT

The authors would like to thank MOSIS for the helps on Process Design Kit

during the course of this research and the fabrication grant of the chip on Aug 20, 2007 at

IBM 7RF fabrication run. We’d also like to acknowledge the Cadence Design Systems

for supplying the Cadence Software under Cadence University Program.

REFERENCES

[1] A. Tekin, M.R.Yuce, W.Liu, “A Low Power MICS Band Transceiver Architecture for Implantable Devices,” Conference Proceedings, IEEE WAMI 2005, Clearwater, FL. [2] A. Tekin, M.R.Yuce, J. Shabani, W.Liu, “A Low Power FSK modulator/demodulator for an MICS Band Transceiver ,” Radio and Wireless Symposium, 17-19 Jan 2006 IEEE, pp159-162. [3] “Class E- A New Class of High-Efficiency Tuned Single-End Switching Power Amplifiers” Nathan O Sokal and Alan D.Sokal, IEEE Journal of Solid state Circuits, Vol. SC-10, No.3, June, 1975 [4] Steve Cripps, RF Power Amplifiers for Wireless Communications, Artech House 1999, pp158-175. [5] RF Micro Devices, Application Notes, AN0001, 1997