Mar/Apr 2003 3

10625 Highstream DrRaleigh, NC 27614kd7o@arrl.net

A High-Performance Digital-Transceiver Design, Part 2

By Jim Scarlett, KD7O

Part 1 of this series looked at some of the system-level designand tradeoffs for a high-performance transceiver that translates

directly from RF to digital. In this installment, we’lllook at the details of the receiver front end.

The first installment of thisseries gave an overview of a high-performance transceiver using

an “almost all digital” approach.1 Whilestill using analog filters and amplifiers,this approach translates directly be-tween RF and digital domains. Designgoals were presented that would meetor exceed the performance of commer-cially manufactured radios.

Here in Part 2, we’ll look at the de-sign details for the receive side of theradio. DSP will not be covered until alater installment, but we’ll look at thereceive signal processor (RSP) hard-ware design here. Considerations for1Notes appear on page 9.

using the ADC will be covered, includ-ing the use of dither and interfacingthe ADC to the RSP. The clock sourcewill get special attention as well.

Analog Processing FirstFirst I’ll describe the analog front

end. The RF amplifier uses ideas thathave been covered before. I’ll describehow those ideas come together in thisdesign. I won’t spend much time on thefilters, since the basic design has al-ready been covered in detail in QEX.2

I mentioned in Part 1 that my fil-ter capacitor values are different fromBill Sabin’s to account for my own ar-eas of interest. I also made some otherchanges regarding components. In theinterest of minimizing size and cost, Iuse NP0 ceramic-chip capacitors in thefilters. These capacitors will be okayfor up to a few watts of input power.

See Fig 1 for the filter schematics. Ca-pacitor values of “0” indicate where theboard has pads for additional capaci-tors to adjust the values while tuningthe filters.

The relays are inexpensive and caneasily handle the required power. Theyalso switch in about 5 ms, so they arecompatible with rapid switchingbetween transmit and receive—or be-tween bands. Additional relays are in-cluded in the filter/amplifier modulefor transmit/receive switching of themodule.

RF Amplifier BoardAs I mentioned in Part 1, I rejected

the use of a common-base amplifier con-figuration because of poor reverse iso-lation. While looking at the amplifierin John Stephensen’s noise blanker,3 Idecided that the topology would meet

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my needs in this area. The desired IP3performance would be achieved througha push-pull transistor pair operating ata higher bias current.

The resulting amplifier is shown inFig 2. A Mini Circuits 1:1 transformergenerates the balanced signal used bythe two transistors. I used someMotorola MRF5811 transistors that Ihad on hand. These devices—basicallyan MRF581 in a SOT-143 package—provide an excellent noise figure whilerunning at high currents. In this ap-

Fig 1—Filter schematics: (A) low-pass; (B) top-coupled band-pass; (C) shunt-coupled band-pass. Values shown are for the20-meter filters. Component values for the other HF bands areavailable on the ARRL Web site. Resistors and capacitors are0805 SMT unless noted. 0 pF capacitors are pads only.LPFL1, L2—0.352 µµµµµH, 8 turns #26 enameled wire on a T50-6powdered-iron toroid coreTop-coupled BPFD1, D2—DL4001K1, K2—PC mount SPDT relay (Digi-Key #G5V-1DC5)L1, L2—0.575 µµµµµH, 10 turns #26 enameled wire on a T50-6powdered-iron toroid coreShunt-coupled BPFD1, D2—DL4001K1, K2—PC mount SPDT relay (Digi-Key #G5V-1DC5)L1, L2—0.657 µµµµµH, 12 turns #26 enameled wire on a T50-6powdered-iron toroid core

plication, they are being operated witha bias current of about 40 mA.

The 20-Ω resistors at the emittersset the bias currents. Along with thefeedback transformers, they deter-mine the input impedance of the am-plifier. The transformers are wound onbinocular ferrite cores. The currentlevels are too high for typically avail-able RF transformers, which shouldnot be substituted. The transformerimpedance ratio also helps set the gainof the amplifier.

The transistors can be powered with+9.5 to +12 V. The higher supply volt-age will improve the IP3 by a couple ofdecibels, but will force the transistorsto dissipate more power. I am operat-ing the prototype at about +10 V. Laterversions will probably have a regulatoron board to generate this voltage.

The 475-Ω resistors provide aproper output match for the filters.Since this resistor is unnecessary inthe biasing scheme, it is ac coupled.Had it been dc coupled, a 1/2-W resis-

Mar/Apr 2003 5

tor (expensive in chip form) wouldhave been required. As it is, a 100-mW0805 resistor is fine (and cheap). Theoutput transformer matches the am-plifier to 50 Ω. The impedance ratioalso helps determine the amplifiergain. The output transformer is a con-ventional broadband transformer witha 16:1 impedance ratio (centertapped), wound on a BN3312-43 core.

The gain of the amplifier was mea-sured to be flat within less than 2 dBacross the HF spectrum, with the leastgain at the high end. The input andoutput match also showed some deg-radation at the high end. Still, theSWR is 2:1 or better across the HFspectrum. One might get better per-formance using transmission-linetransformers, but I did not try this. As

Fig 2—RF amplifier schematic diagram. Resistors and capacitors are 0805 SMT unless noted.C11—1 µµµµµF, 25-V, X7R, 1206 SMT capacitorD1, D2—DL4001J1, J2—2-pin headerJ3, J4—PC mount SMB bulkhead jack(Digi-Key #J522)

K1, K2—PC mount SPDT relay (Digi-Key#G5V-1DC5)Q1, Q2—MRF5811 NPN transistorR1, R2—2 kΩΩΩΩΩ, 10-turn trim pot (Digi-Key#3214W-202ECT)R9, R10—56.2 ΩΩΩΩΩ, 1210 SMT resistor

T1, T2—6 t primary, 3 t secondary on aBN202-61 binocular ferrite coreT3—1:1 transformer (Minicircuits ADT1-1)T4—8 t center-tapped primary, 2 tsecondary on a BN3312-43 binocularferrite core

is, the total gain of the front end at20 meters was measured to be justover 6.8 dB, which is close enough tothe 7 dB used in the spreadsheet inPart 1.

As shown in the block diagram(Fig 8 of Note 1), there are two RF am-plifiers. One is used for the lower HFbands and both are used on the higherbands. The preamplifier used on thehigher bands can be switched in or outusing the relays on the board. I optedto leave the second RF amplifier in lineat all times and therefore did not popu-late the relays or control circuitry.Jumpers were installed across the re-lay pads.

I have not yet measured the IP3 ofthis amplifier, but my simulation inSerenade SV4 gave better than

+44 dBm. Because the reverse isola-tion is very high, this value should notsuffer much even when terminated bythe band-pass filters.

RF to DigitalAt the heart of this receiver archi-

tecture is the AD6645 analog-to-digi-tal converter. The design for the ADCboard is quite straightforward, asshown in Fig 3. Notice that all inputsto the ADC are differential. This isnecessary for all devices of this type ifyou are to get maximum performance.Even with much less-precise parts, thenoise and distortion performanceabove a few megahertz will degrade ifyou use a single-ended input.

Local regulation is provided to re-duce noise-pickup issues. Decoupling

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Mar/Apr 2003 7

capacitors are placed as closely aspossible to each power pin. Small (0603)capacitors are used to allow placementon the same side of the board as theADC. At this resolution and speed, evenusing vias to decoupling capacitors onthe bottom of the board can degradeconverter performance, according to theapplications engineers at ADI.

The clock input is terminated to pro-vide a 50-Ω match to the synthesizer. A1:4 transformer converts the input to adifferential signal, which is then clippedby the diode pair and applied to theADC. As described in the AD6645datasheet, the diode clipping preventslarge voltage swings that can feedthrough to other parts of the device. Italso helps reduce noise susceptibility.

Similarly, the analog inputs to theADC are provided differentially via atransformer. The 24.9-Ω series resis-tors isolate the transformer from theADC inputs. Notice that the 1-kΩ dif-ferential input impedance is not fullymatched. Instead, the input signal istransformed up to 200 Ω. The result isthat the full-scale input is about+4.8 dBm. Remember that the ADC isa voltage device—we don’t need toworry about mismatch power losses.A termination resistor provides theproper match to the 50-Ω source.

The dither signal is also summed atthe input node, via a 1-kΩ resistor. Thisimpedance minimizes loading of theinput and divides the signal down tothe appropriate level. The datasheetrecommends a dither power level ofabout –19 dBm. I thought about a sim-pler-looking idea where the ditherwould be injected at a center tap on thetransformer secondary. However, asBrad Brannon, N4RGI, pointed out, thisresults in a balanced noise signal thatnegates the effectiveness of dither.

Output signals are series terminatedto minimize dynamic currents at theoutput pins, which can reflect back anddisrupt part performance. The termina-tion resistors also help improve thequality of the signals at the buffer in-put. These termination resistors shouldbe as close to the output pins as pos-sible, which is why I used small sur-face-mount resistor arrays.

The output buffer was chosen forits timing characteristics: in particu-lar, the skew between the bits (0.5 ns).The timing window between the clockand data signals at the RSP is verytight. Excessive variation between theRSP clock and the incoming data canresult in bad data due to timing viola-tions. The DRY signal from the ADCmeets the timing requirements for theRSP clock, as long as additional varia-tion is not introduced. By sending thissignal through the same buffer as thedata lines (since they only take up 14of 16 bits), the variation is minimizedand proper timing is guaranteed.

An important aspect of ADC per-formance is the quality of the encodeclock and the aperture jitter of the con-verter itself. If the level of jitter on theclock or in the sample-and-hold circuitof the ADC is too high, it can directlyaffect the noise performance of theconverter. This topic was discussedbriefly in Part 1; but after further re-flection, I felt that the explanation wassomewhat confusing. Some of the feed-back I received confirmed this. There-fore, a discussion is included in thesidebar “Jitter and ADC Performance.”

A Low-Noise ClockThe ADC used in this architecture

is subject to the same problems witha noisy local oscillator as a traditionalanalog design. In the traditionaldesign, the problem is known as re-ciprocal mixing. Here, we have a deg-radation of the S/N caused by clock jit-ter. The result is the same, with noisesidebands appearing on the incomingsignals. If the oscillator is noisyenough, these sidebands may mask adesired weak signal. This is discussedmore thoroughly in the jitter sidebar.

One advantage of this architectureis that the tuning is done digitallywithin the RSP. Therefore, the “localoscillator” can actually be a low-noisecrystal oscillator instead of the typi-cal wide bandwidth VCO.

The oscillator design (Fig 4) is basedclosely on the design John Stephensenpresented in QEX.5 For the most part, Ijust altered components for the fre-quency difference, or for ease of procure-ment. The operating frequency is64.96 MHz, which is phase-locked to a12.992-MHz reference. The ADC fre-

quency was chosen to allow integer deci-mation to both 40 kHz (for FM) and16 kHz (for SSB and CW).

The key to John’s design is the in-put level in the JFET. In this configu-ration, the impedance of the FET isfairly high (50-100 Ω). Therefore, sincethe same RF current flows in the reso-nator and FET, the oscillator inputpower is higher than the power dissi-pated in the resonator. For a givenresonator power, most common oscil-lator designs extract much less. Thehigher power leads directly to lowerphase noise, per Leeson’s equation.

Approximately +8 dBm is availableto the ADC after the 3-dB attenuator.A buffered output from the emitter fol-lower is also attenuated to provide thecorrect level to the PLL chip. The PLLused is the ADF4001, which is designedspecifically for clock applications below200 MHz. There is no prescaler andthere are no minimum division ratiosfor either the RF or reference frequency.

Other advantages of this device arethe very low phase-noise floor and thatthe phase/frequency discriminator(PFD) can be used up to 100 MHz.In this application, we’ll use it at12.992 MHz with no reference divi-sion. The higher frequency in the PFDhelps lower the noise floor within theloop bandwidth. For example, doublingthe reference frequency increases thePFD noise by 3 dB, but the multipliernoise is reduced by 6 dB. Here, thePLL noise floor is about –128 dBc/Hz,and the VCXO noise will dominateoutside the loop bandwidth of about230 Hz. Close-in (inside about 100 Hz),the noise will be determined by thereference oscillator. The jitter sidebarprovides additional details for the pre-dicted clock performance.

Cheap and Easy DitherThere are two main ways to gener-

ate large-scale dither for the ADC. Onethat is commonly used in commercialapplications—such as test equip-ment—involves digitally generatingpseudorandom noise. This wide-bandnoise is then injected into the front endof the ADC, and subsequently sub-tracted from the digital result. Thesecond alternative is to inject narrow-band noise that is outside the bandsof interest. This method is used here.

The dither circuit is shown inFig 5. It is based on a circuit presentedin the manual for Analog Devices’ HighSpeed Design Techniques seminar. Iopted to use op amps throughout in-stead of the variable-gain amplifierspresented in that discussion.6 I alsoused an op amp with a higher inputimpedance (the AD8055), which allowsme to use a larger resistor for my noise

Fig 3—ADC schematic diagram. Resistorsare 0805 SMT unless noted. Capacitors are0603 SMT unless noted.C9—0.01 µµµµµF X7R 0805 SMT capacitorC21—1 µµµµµF, 16-V X7R 1206 SMT capacitorC22-25—10 µµµµµF, 16-V tantalum capacitorD1—Dual Schottky diode, seriesconfiguration, SOT23 (ZC2812E, BAS70-04)J1, J2—2-pin headerJ3—DB25 right-angle, PC mount (Digi-Key#A23285)J4-6—PC mount SMB bulkhead jack (Digi-Key #J522)RA1, RA2—Resistor array, 8 ×××××470 ΩΩΩΩΩ (Digi-Key #742C163471)T1—1:4 transformer (Mini Circuits ADT4-6)T2—1:4 transformer, CT (Mini CircuitsADT4-6T)U1—16-bit buffer with integratedtermination resistors, SSOP,74LVTH162244DLU2—High-speed ADC, AD6645ASQ-80U3—3.3-V low-dropout voltage regulator,Analog Devices ADP3338AKC-3.3U4—5.0-V low-dropout voltage regulator,Analog Devices ADP3338AKC-5.0

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source. This requires less total gain andreduces the variation in the noise lev-els, as the resistor noise dominates.Additional variation in generated noisecan be caused by part-to-part differ-ences in the op amp’s current noise. Thethird amplifier stage has adjustablegain to set the proper level.

The noise generator (first threestages) is followed by an active low-passfilter. This filter has a bandwidth ofabout 450 kHz; with six poles, it reducesthe injected noise below the noise floorat 160 meters. Within that constraint,

the bandwidth is enough to minimizethe gain required to achieve the correctnoise power, and makes sure the noiseis random rather than sinusoidal. Theoutput of the final filter stage drives abuffer that has a gain of two.

The AD8055 amplifier is a high-speed device, with a 3-dB bandwidth ofover 300 MHz. This is helpful in twoways. First, with the high gains in-volved, the actual bandwidth of theamplifiers ends up being only a fewmegahertz. Second, the output imped-ance of an op amp increases with fre-

quency. This allows the noise signal aforward path through the filter feed-back capacitors, since the op ampoutput is no longer an ideal, zero-im-pedance voltage source. The result isthat the ultimate rejection of the filtersis limited. The AD8055 output imped-ance remains very low into the VHFrange, thus minimizing this effect.

Receive Processing HardwareThe hardware implementation of the

Receive Signal Processor (RSP) is fairlysimple. See Fig 6. At this point, the sig-

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Fig 4—Receive PLL schematic diagram. Resistors and capacitors are 0805 SMT unlessnoted.

C1—0.015 µµµµµF polyester capacitor (Digi-Key#P10957)C2-4—0.01 µµµµµF 0603 SMT capacitorC10—0.027 µµµµµF polyester capacitor (Digi-Key #P10960)C11—0.12 µµµµµF polyester capacitor (Digi-Key#P10967)C20—1 µµµµµF polyester capacitor (Digi-Key#P10979)C21, C24—1 µµµµµF, 25-V, X7R, 1206 SMTcapacitorC22, C23—1 µµµµµF, 16-V, X7R, 1206 SMTcapacitorC28—3-10 pF trimmer capacitor, SMT(Digi-Key #SG2002)J1—2-pin headerJ2—DB9 right angle, PC mount (Digi-Key#A23303)

J3, J4—PC mount SMB bulkhead jack(Digi-Key #J522)L1—0.39 µµµµµH, 1210 SMT (Digi-Key #M6100)L2—1.5 µµµµµH, 1210 SMT (Digi-Key #M6107)L3, L4—2.2 µµµµµHL5—12 turns #28 enameled wire on a T37-12 powdered-iron core, tap 3 turns fromcold endT1—primary 6 turns #28, secondary 2turns #28 on a BN2402-61 binocular ferritecoreU1—PLL, ADF4001BRUU2—5-V voltage regulator, SOT89,78L05UAU3—12-V voltage regulator, SOT89,78L12UAY1—64.96 MHz, third-overtone(International Crystal)

nal has been digitized, so we only needbe concerned with signal integrity, pri-marily on the input side. At the output,the serial interface only needs to be fastenough to get the I/Q words out at amaximum 40-kHz rate for DSP process-ing by another computer. Signal integ-rity is easy at this speed, but we stilluse proper buffering and a series ter-mination to keep everything clean.

The RSP is initialized and con-trolled using the parallel Microportinterface. The serial interface can beused for control after setup, but can-not be used for initialization. Since theparallel interface is necessary anyway,I thought it would be simpler to use itexclusively and to use the serial portonly for the signal path. I also wanted

to use the DSP for signal processingonly, not for housekeeping. TheMicroport interface is set to mode 0 inhardware by grounding the MODE pin.

Grounding the PAR/SER pin selectsthe serial interface for output data.The serial word length is set to 24 bits,which transfers all of the data butminimizes overhead. The RSP is theserial master, so control signals aregenerated in the RSP and sent to theDSP serial port. The serial clock is setto its minimum value, which meets thebandwidth requirements for a 40-kHzoutput using 24-bit I/Q words.

The actual use of the RSP functionsis more closely related to the DSP thanto the analog front end. Therefore, I willspend more time in the DSP install-

ment discussing RSP operation than Iwill here. The RSP will be set up to pro-vide I/Q data at a sampling rate of 16kHz for SSB/CW and 40 kHz for thewider-bandwidth modes (AM/FM). Thegoal was to get better than 100-dB out-of-band rejection. The high decimationrates make this a challenge in the RSP,but it can be done with the chosen out-put rates. I’ll go into my thoughts in thisarea more in the DSP installment.

SummaryIn this installment, we looked at the

design details for an analog front endthat should meet the requirementslaid down in Part 1. Some of the ideashave been seen in these pages before.The key, as always, is to ensure thatthe tradeoffs are managed to allowmaximum performance.

The AD6645 ADC is at the heart ofthe receiver architecture. This parthas excellent noise and distortion per-formance, which allows this architec-ture to work. Low aperture jitter helpsto minimize the ADC equivalent ofreciprocal mixing, further enhancingperformance. Further improvementsof ADCs in the future will allow evenbetter system performance, and themodular design will allow us to takeadvantage of this. For now, however,the performance available from theAD6645 is the state of the art.

In the next installment, we will lookat the transmit side of the transceiver.Just as the receiver has been helpedby improvements in ADCs, newerhigh-speed DACs allow excellenttransmitter performance. The detailsof integrating them into the transmit-ter will be covered in Part 3.

AcknowledgementsI would like to thank Doug Smith,

KF6DX; Paul Smith and GaryHendrickson for their input on topicsrelated to this article.Notes1J. Scarlett, KD7O, “A High-Performance

Digital Transceiver Design, Part 1,” QEX,Jul/Aug 2002, pp 35-44.

2W. Sabin, WØIYH, “Narrow Band-Pass Fil-ters for HF,” QEX, Sep/Oct 2001, pp 13-17.

3J. Stephensen, KD6OZH, “The ATR-2000:A Homemade, High-Performance HFTransceiver, Part 2,” QEX, May/Jun 2000,pp 39-51.

4Available at www.ansoft.com .5J. Stephensen, KD6OZH, “A Stable, Low-

Noise Crystal Oscillator for Microwave andMillimeter-Wave Transverters,” QEX, Nov/Dec 1999, pp 11-17.

6Analog Devices, High Speed Design Tech-niques, 1996, pp 5.41-5.48.

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Fig 5—Dither-generator schematic diagram. Resistors and capacitors are 0805 SMTunless noted otherwise.

AR1-7—High-speed op amp, AD8055ARTC19, 21—10 µF 16-V tantalum capacitorC25-28—1 µµµµµF, 16-V, X7R, 1206 SMTcapacitorJ1—3-pin headerJ2—PC mount SMB bulkhead jack (Digi-Key #J522)

Fig 6(right) —Receive Signal Processorschematic diagram. Resistors andcapacitors are 0805 SMT unless noted.C9, C10—10 µµµµµF, 16-V tantalum capacitorJ1—2-pin headerJ2, J3—DB25 right angle, PC mount (Digi-Key #A23312)J4—DB9 right angle, PC mount (Digi-Key(#A23303)RA1—Resistor array, 4 ×××××100 ΩΩΩΩΩ (Digi-Key#742C083101)U1—Quad buffer, 74ALVC125PWU2—RSP, AD6620ASU3—3.3-V low-dropout voltage regulator,Analog Devices ADP3338AKC-3.3

R15—500 ΩΩΩΩΩ, 10-turn trim pot (Digi-Key#3214W-501ECT)U1—5-V voltage regulator (positive),SOT89, 78L05UAU2—5-V voltage regulator (negative),SOT89, 79L05UA

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Phase Noise and ADC Performance

Table 1—Predicted Receive PLL Phase-NoisePerformance

Offset Phase Noise(Hz) (dBc/Hz)10 –9520 –10450 –115100 –125200 –128500 –1381 k –1472 k –1555 k –16310 k –16720 k –16950 k –170100 k –171

There was some confusion from the discussion of clockjitter in Part 1 of this series. This led me to reevaluate howthe material was presented and is the reason for thissidebar. One of the problems was making a connectionbetween phase noise and clock jitter. Therefore, this dis-cussion will be primarily focused on phase-noise require-ments, and I will only discuss the relationship with clockjitter as necessary.

Rather than generating arbitrary jitter specifications,let’s look at actual system requirements and translate thisto a clock phase-noise requirement. Measurements areusually termed “noise-limited” when reciprocal mixinghas increased the system noise figure by 1 dB. In ourcase, this would happen if the SNR of the converter in-creases by 1 dB.

Initial measurements with an evaluation board for theAD6645 showed a value for the SNR at 30 MHz of about75 dB. We’ll use this number for our calculations. We’llalso do the calculations for 10 meters, since Eq 2 inPart 1 shows that jitter has a greater effect on higher fre-quency signals. For this discussion, we’ll ignore that jitteron the clock or input signal during the SNR measurementmay have had a significant contribution to the 75 dB SNRand assume this measurement was “jitterless.”

In order to keep the SNR from increasing by 1 dB, theSNR contribution from jitter must be better than 81 dB.Thus, over the Nyquist bandwidth (1/2 of the samplingrate), the integrated noise due to jitter must be less than–81 dBc. For the purposes of this discussion, the carrieris assumed to be full-scale (approximately –13 dBm atthe receiver input on 10 meters).

Using Eq 1 from Part 1 (processing gain), the requirednoise applied by the clock to the incoming signal must beless than –156.1 dBc/Hz. The clock rate is 64.96 MHz inthis calculation. However, this is not the required clocknoise performance, because of the relationship

SNR = 20 log[ωclk

/ (σclk

ωsig

)] (Eq 1)

where σclk is the frequency jitter of the clock and equalsσtωclk. This relationship shows that if the potential inter-fering signal is lower in frequency than the clock, thenoise sidebands are improved based on the ratio. Like-wise, noise sidebands applied to a signal that is higher infrequency than the clock are worse than the clock itself.

Thus, for a 64.96-MHz clock and a 28.5-MHz incomingsignal at full scale, the clock noise requirement is–149 dBc/Hz to meet our noise specification. That is, theaverage noise level integrated over our desired band-width at a given offset from the interfering signal must bebetter than –149 dBc/Hz. Assuming a constant sidebandslope (not true at PLL corner frequencies), that wouldmean that the noise must meet this specification at thecenter of the desired passband. We can use this to de-termine how our clock’s predicted performance measuresup.

Also, notice that the above requirements are for10 meters. The requirements would be less stringent at20 meters (about 6 dB), because jitter has a smaller ef-fect at lower frequencies. Likewise, the requirementswould be much more difficult at 2 meters (about 14 dB).This is offset by the fact that close-in signals tend to bemuch stronger at HF than on 2 meters. This is importantas I consider whether to adapt this radio for 2 meters(undersample the third Nyquist zone) or to simply use atransverter.

On a separate note, by solving Eq 1 for jitter, we findthat the jitter requirement is 0.5 ps at 10 meters, not the0.1 ps example used in Part 1. At 2 meters, meeting thesame specifications would require 0.1 ps jitter.

Clock PerformanceTable 1 shows the expected performance of the re-

ceive PLL. The VCXO and reference were modeled us-ing ‘typical’ expected values for crystal parameters(except the maximum Rs of 40 Ω for the VCXO crystaland 25 Ω for the reference crystal) and the maximumspecification for FET resistance. This should give a rea-sonably conservative model. I did the model usingLeeson’s equation on an Excel spreadsheet.

The noise floor within the PLL was determined usingthe ADF4001 datasheet. The specified noise floor for thePFD is –153 dBc/Hz at a comparison frequency of 1 MHz.Using a reference frequency of 12.992 MHz (with a 10 logrelationship) and a multiplication of 5 (with a 20 log rela-tionship) results in a PLL noise floor of approximately–128 dBc/Hz.

At offset values above the loop frequency of 230 Hz,the VCXO noise dominates, and below about 100 Hz,reference noise does. Between these offsets, the PLL isthe primary noise source.

The table shows that we meet the required noise speci-fications at an offset of about 1200 Hz. This means that afull-scale signal outside of the 2400 Hz SSB passbandwill have no significant reciprocal mixing effects. For a500-Hz CW bandwidth, a full-scale signal offset less than1200 Hz from the center of the passband can cause re-ciprocal mixing, but an S9+40 signal outside the pass-band would not cause noticeable degradation. For thelower HF bands, these results are even better, while at2 meters, a 5 kHz offset would be required for no signifi-cant effects from a full-scale signal.

This example shows a distinct advantage to this re-ceiver architecture with respect to reciprocal mixing.Since the tuning is done digitally, we can use a low-noisecrystal oscillator that drastically reduces reciprocal mix-ing effects. Between this and the outstanding noise andjitter performance of the AD6645 converter, we can virtu-ally eliminate reciprocal mixing as a problem in our HFreceiver. This example also demonstrates why reciprocalmixing from close-in signals is so difficult to tackle in re-ceivers with wide-band, general coverage VCOs.

!!