6-9 ghz low-noise amplifier design and implementation543794/fulltext01.pdf · low-noise amplifier...
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Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings Universitet SE-601 74 Norrköping, Sweden 601 74 Norrköping
LiU-ITN-TEK-A--10/047--SE
6-9 GHz Low-Noise AmplifierDesign och Implementering
Mohammad Billal Hossain
2010-06-14
LiU-ITN-TEK-A--10/047--SE
6-9 GHz Low-Noise AmplifierDesign och Implementering
Examensarbete utfört i Electronicsvid Tekniska Högskolan vid
Linköpings universitet
Mohammad Billal Hossain
Handledare Adriana SerbanExaminator Adriana Serban
Norrköping 2010-06-14
Upphovsrätt
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© Mohammad Billal Hossain
6-9 GHz Low-Noise Amplifier Design and Implementation
Mohammad Billal Hossain
June 14, 2010
i
Preface
This report is the result of Master of Science Thesis carried out at the Department of
Science and Technology (ITN) in Linköping University.
I would like to take a chance to thank the people who have helped and encouraged
me during this Master Thesis work. First of all, I want to express my gratitude to
Adriana Serban, for giving me the opportunity to perform my Master Thesis at ITN
department and for being my supervisor. This thesis work could not have been
accomplished without her guidance and full assistance. I would also like to thank
professors in ITN department Shaofang Gong, Magnus Karlsson and Allan Huynh
for their suggestion and comments.
ii
Abstract
Low-noise amplifier design (LNA) is a critical step when designing a receiver front-
end. For the broadband technologies and particularly ultra-wideband (UWB) system,
designing the LNA becomes more challenging. This master thesis mainly focuses on
the LNA design for the European UWB recommendation, i.e. LNA covering the 6 - 9
GHz spectrum. Moreover, better understandings of the design process in correlation
with the implementing of the LNA on a printed circuit board (PCB) were expected.
The LNA was manufactured, assembled and measured with network analyzer. This
report presents a complete functional design of an UWB LNA.
iii
List of Abbreviations
ADS Advanced Design System
BPFs Bandpass Filters
BW Bandwidth
CAD Computer Aided Design
EDA Electronic Design Automation
EMI Electromagnetic Interference
EIRP Equivalent Isotropically Radiated Power
FCC Federal Communication Commission
FM-UWB Frequency Modulation UWB
GaAs Gallium Arsenide
HBTs Hetero-junction Bipolar Transistors
HEMTs High Electron Mobility Transistors
JFETs Junction Field Effect Transistors
LNA Low-Noise Amplifier
MC-UWB Multi Carrier UWB
MW Microwave
NF Noise Figure
OFDM Orthogonal Frequency Division Multiplexing
PSD Power Spectral Densities
RF Radio Frequency
RFI Radio Frequency Interference
RFID Radio Frequency Identification
RSC Radio Spectrum Committee
SMDs Surface Mount Devices
S-parameters Scattering Parameters
UMTS Universal Mobile Telecommunication System
UWB Ultra-wideband
VSWR Voltage Standing Wave Ratio
WPAN Wireless Personal Area Network
iv
List of Figures Figure 2- 1 Diagram of band allocation [7]
Figure 2- 2 FCC emission limit for outdoor UWB communications [3]
Figure 2- 3 FCC emission limit for indoor UWB communications [3]
Figure 2- 4 Spectrum of the Main Interfering Communication Standards for UWB
Communication System [11]
Figure 2- 5 Skin depth area of a wire [13].
Figure 2- 6 Electric equivalent circuit representation of the resistor [15].
Figure 2- 7 Absolute impedance value of a 500 ohm thin-film resistor as a function of
frequency [15].
Figure 2- 8 Electric equivalent circuit for a high frequency capacitor [15].
Figure 2- 9 Absolute value of the capacitor impedance as a function of frequency
[15].
Figure 2- 10 Distributed capacitance and series resistance in the inductor coil [4].
Figure 2- 11 Equivalent circuit model of the HF inductor [15].
Figure 2- 12 Frequency response of the impedance of an RFC [15].
Figure 2- 13 Biasing effect of n-channel JFET [21]
Figure 2- 14 IV characteristic of FET [23].
Figure 2- 15 GaAs MESFET [5]
Figure 2- 16 HEMT [16]
Figure 2- 17 High frequency FET model [22]
Figure 2- 18 Segment of transmission line expressed with distributed parameters R,
L, C and G, where all parameters are given in terms of unit length [4].
Figure 2- 19 Terminated transmission line at location z=0.
Figure 2- 20 (a) Microstrip line; (b) end view of microstrip line [9].
Figure 2- 21 Line voltages reference to the load end [21]
Figure 2- 22 Smith Chart.
Figure 2- 23 Parametric representation of the normalized resistance r [15].
Figure 2- 24 Parametric representation of the normalized reactance x [15].
Figure 2- 25 Smith chart by combining r and x circles for 1≤Γ [15].
Figure 2- 26 Reflection coefficient: A = (0.8-j1.6), angle BOC=-55.5 degree [21].
Figure 2- 27 T network connected to the base-emitter input impedance of a bipolar
transistor. Assuming 500 =Z ohm and 2=cf GHz [15]
Figure 2- 28 Computation of the normalized input impedance of the T network
Figure 2- 29 Two-port network [15].
Figure 2- 30 Two port scattering network with source and load [21]
Figure 3- 1 RF receiver using a heterodyne architecture [5].
Figure 3- 2 Thermal noise [7]
Figure 3- 3 Shot noise [7]
Figure 3- 4 Representation of noise by input noise generators [7].
Figure 3- 5 Simplified single stage amplifier [3]
Figure 3- 6 Eight possible two components networks [3].
Figure 3- 7 Impedance effects of series and shunt connections of L and C [3].
Figure 4- 1 Minimum noise figure, associated gain vs. frequency characteristics [3].
v
Figure 4- 2 ADS Simulation setup for the I-V characteristic using electrical model of
NE3512S02.
Figure 4- 3 Simulated I-V Characteristic of NE3512S02.
Figure 4- 4 I-V Characteristic of NE3512S02 according to data sheet [3]
Figure 4- 5 Simulation setup for the Electrical and S-Parameter model of
NE3512S02.
Figure 4- 6 S-Parameters are estimated using Electrical (Thick line) and S-Parameter
model (Thin line) at the Q-point (ID = 20 mA and VDS = 2 V).
Figure 4- 7 Fixed-bias Configuration [7]
Figure 4- 8 Self-bias Configuration [7]
Figure 4- 9 Active-bias Configuration [8].
Figure 4- 10 Layout component of footprint for the transistor (NE3512S02) and three
types of packages such as 0402, 0603 and 0805.
Figure 4- 11 Different layout components of via hole model and ADS via model.
Figure 4- 12 ADS set-up for via simulation.
Figure 4- 13 Reflection coefficients for different via models.
Figure 4- 14 Impedance vs Frequency. Solid line represents for ATC100A101
(100pF) and dot line for ideal 100 pF capacitor [11] .Figure 4- 14 Impedance vs
Frequency. Solid line represents for ATC100A101 (100pF) and dot line for ideal 100
pF capacitor [11] .
Figure 4- 15 Insertion loss (S21) of ATC100A101 (100 pF) capacitor [11].
Figure 4- 16 Kemet COG ceramic capacitor model schematic [12].
Figure 4- 17 Kemet X7R ceramic capacitor model schematic [12].
Figure 4- 18 Murata Monolithic ceramic SMT Capacitor model [12].
Figure 4- 19 CAPP2 (Chip capacitor) model for ATC [12].
Figure 4- 20 Forward transmission vs frequency characteristics for 1 pF capacitor
dofferent companies such as Kemet, ATC, Philips and Murata.
Figure 4- 21 Forward Transmission vs Frequency characteristic of Kemet capacitor
model with different values.
Figure 4- 22 Forward Transmission vs Frequency for Bypassing Kemet capacitor
model. Thick line for C1 and thin line for C2 to C4
Figure 4- 23 Three types of RF choke [13].
Figure 4- 24 ADS set-up for RF choke using quarter wave stub.
Figure 4- 25 RF choke using radial stub.
Figure 4- 26 RF choke using butterfly stub.
Figure 4- 27 Forward transmission vs frequency characteristics of different types of
RF chokes (Thick line for Butterfly, Thin line for quarter wave line and Das line for
radial).
Figure 4- 28 Forward transmission vs frequency with different terminated values in
port 3 (Das line for 5 ohm, star line for 10 ohm thin line for 20 ohm and thick line for
50 ohm).
Figure 4- 29 Complete Schematic of RF choke with bias arrangement.
Figure 4- 30 Forward transmission vs frequency characteristic for the schematic of
Figure 4- 29.
Figure 4- 31 Schematic of the NE3512S02 S-parameter model before stabilization.
Figure 4- 32 Stability factor vs frequency before stabilization.
Figure 4- 33 Power gain and noise figure before stabilization.
vi
Figure 4- 34 Annotation of DC simulation of stabilized FET (Electrical model) fixed
bias (IDS=20 mA and VDS=2V, VGS=-0.17V) circuit without matching network.
Figure 4- 35 Schematic of stabilized FET(S-parameter model) without matching
network.
Figure 4- 36 Stability factor vs frequency characteristic after stabilization with S-
parameter model.
Figure 4- 37 Power gain and noise figure after stabilization with S-parameter model.
Figure 4- 38 Layout component.
Figure 4- 39 Matching for noise figure at 8.5 GHz.
Figure 4- 40 Smith chart of input matching network by lumped elements.
Figure 4- 41 Input matching network where L1=1.54 nH, L2=1.87 nH, L3=1.02 nH,
L4=1.11 nH,C1=1.2 pF, C2=1.5 pF, C3=1.55 and C4=0.42 pF pF.
Figure 4- 42 Matching condition at 8.5 GHz after putting input matching network.
Figure 4- 43 Comparison between Noise figure (star line) and minimum noise (solid
line).
Figure 4- 44 Input matching network with microstrip, L1=2.1 mm, L2=2 mm, L3=2
mm, L4=3.5 mm, L5=3.57 mm, L6=1.25 mm, L7=2.38 mm and W=0.524 mm.
Figure 4- 45 Power gain and noise figure (star line) vs frequency with input matching
network.
Figure 4- 46 Matching condition at 8.5 GHz after putting input microstrip matching
network.
Figure 4- 47 Output matching network with microstrip line, L1=2 mm, L2=7 mm,
L3=2 mm, L4=2.5mm, L5=3mm, L6=2 mm, L7=4mm and W=0.524mm.Figure 4- 1
Minimum noise figure, associated gain vs. frequency characteristics [3].
Figure 4- 48 Power gain and noise figure (star line) vs frequency with input and
output network.
Figure 4- 49 LNA before matching network.
Figure 4- 50 Simulation result of LNA at 8.5 GHz matching point without matching
network.
Figure 4- 51 Smith chart for IMN design at 8.5 GHz.
Figure 4- 52 IMN at 8.5 GHz before optimize.
Figure 4- 53 IMN at 9 GHz after optimize.
Figure 4- 54 Simulation result of LNA with IMN after optimization.
Figure 4- 55 Smith chart for OMN design at 9 GHz.
Figure 4- 56 OMN at 9 GHz before optimize.
Figure 4- 57 Simulation result of LNA with optimized IMN and unutilized OMN.
Figure 4- 58 OMN at 9 GHz after optimization.
Figure 4- 59 LNA with optimize IMN and OMN at 9 GHz.
Figure 4- 60 Simulation result of LNA with IMN and OMN.
Figure 4- 61 complete layout look like LNA with IMN and OMN.
Figure 4- 62 Forward transmission (solid line) and transducer gain (dot line).
Figure 4- 63 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220
pF, C4=100nF and R1=43 Ω.
Figure 5- 1 Schematic for VIA model simulation.
Figure 5- 2 Input reflection coefficient of different via models of Figure 5- 1.
Figure 5- 3 Schematic for SMT capacitor model simulation.
vii
Figure 5- 4 Forward transmission vs frequency characteristics for 10 pF capacitor,
Kemet-solid line star, ATC-circle line, Philips-star line and Murata-triangle line.
Figure 5- 5 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF,
C4=100nF and R1=43 Ω.
Figure 5- 6 Forward transmission vs frequency simulation result of Figure 5- 5.
Figure 5- 7 Forward transmission vs frequency simulation result of Figure 5- 5.
Figure 5- 8 Input reflection coefficient vs frequency simulation result of Figure 5- 5.
Figure 5- 9 Simulation setup of the LNA module-1with input and out put matching
networks.
Figure 5- 10 Power gain vs frequency of LNA module-1.
Figure 5- 11 NF vs frequency (LNA module-1); star line- actual noise and solid line-
minimum noise.
Figure 5- 12 Simulation setup of the LNA module-2 with input and output matching
network at 8.5 GHz
Figure 5- 13 Power gain vs frequency of LNA module-2
Figure 5- 14 NF vs frequency (LNA-modele-2); star line- actual noise and solid line-
minimum noise
Figure 5- 15 Simulation setup of the LNA with input and out put matching networks.
Figure 5- 16 Power gain vs frequency.
Figure 5- 17 Noise figure vs frequency; star line- actual noise and solid line-
minimum noise.
Figure 5- 18 Power gain vs frequency; solid line at 8.5 GHz matching and dot line at
9 GHz matching.
Figure 5- 19 Noise figure vs frequency; dot line-for 9 GHz and solid line-8.5 GHz
Figure 5- 20 Complete layout of LNA module-1; C1, C2, C3, C7=10 pF; C4, C8=100
pF; C5, C9=220 pF; C6, C10=100 nF.
Figure 5- 21Complete layout of LNA module-2; C1, C2,C3, C7=1.5 pF; C4, C8=3
pF; C5, C9=10 pF; C6, C10=100 pF. R1=3.9 ohm, R2=10 ohm, R3=150 ohm and
Q1= NE3512S02
Figure 5- 22 Schematic for data display of measured LNA modele-1.
Figure 5- 23 Power gain of the LNA after implementation.
Figure 5- 24 Schematic for data display of measured LNA modele-2
Figure 5- 25 LNA module-2
Figure 5- 26 Comparison between LNA module -1 and -2. Solid line for LNA
module -1 and star line for module -2.
Figure 5- 27 LNA post manufactured simulation
Figure 5- 28 Power gain vs frequency
Figure 5- 29 Noise figure
viii
Contents
Preface …………………………………………………………………………...……i
Abstract …………………………………………………………………………..…. ii
List of Abbreviations ……………………………………………………………......iii
List of Figures …………………………………………………………………...…. iv
Contents ……………………………………………………………………...…….viii
1. Introduction …………………………………………………………………….1
1.1. Background …………………………………………………………….…….1
1.2. Purpose …………………………………………………………………….....1
1.3. Task ……………………………………………………………………..……2
1.4. Outline ………………………………………………………………….…….2
References
2. Ultra-wideband and General RF Theory ……………………………….…3
2.1. Ultra-wideband ……………………………………………………………….3
2.1.1. History of UWB ………………………………………………...……3
2.1.2. UWB Theory …………………………………………………………4
2.1.3. Regulations …………………………………………………………...6
2.1.4. Applications …………………………………………………………..6
2.2. RF Passive Components ……………………………………………………...7
2.2.1. Wire …………………………………………………………………..7
2.2.2. Resistors …………………………………………………………..….8
2.2.3. Capacitor ……………………………………………………………..9
2.2.4. Inductor ……………………………………………………………..10
2.3. Active Devices ……………………………………………………………...12
2.3.1. JFETs ………………………………………………………………..12
2.3.2. GaAs MESFETs …………………………………………………….13
2.3.3. HEMTs ……………………………………………………………...13
2.3.4. FET Transistor Modeling …………………………………………...14
2.3.4.1. High Frequency Model of FET…………………………..….15
2.4. Transmission Line …………………………………………………………..15
2.4.1. Lossless Transmission Line ……………………………………...….17
2.4.2. Voltage Reflection Coefficient …………………………………...…17
2.4.3. Standing Wave Ratio …………………………………………….….18
2.5. Microstrip Transmission Line ……………………………………………....18
2.6. Transmission Line as Electrical Elements ……………………………….…19
2.6.1. Transmission Line as a Reactance ………………………………….21
2.6.2. Transmission Line as a Transformer …………………………….….21
2.7. Smith Chart ………………………………………………………………....22
2.7.1. Smith Chart Theory ……………………………………………..…..23
2.7.2. Smith Chart Applications ………………………………………..….25
2.8. Networks model …………………………………………………………….26
ix
2.8.1. Two-port Networks …………………………………………………27
2.8.2. S-parameters ………………………………………………………...28
References
3. Low-Noise Amplifier ……………………………………..…………….…..31
3.1. Receiver Overview ………………………………………………….…...….31
3.2. Stability ……………………………………………………………………..32
3.3. Noise Analysis ……………………………………………………………....32
3.3.1. Internal Noise Sources ………………………………………………32
3.3.2. Noise Figure ………………………………………………………...34
3.4. Power Gain ………………………………………………………………….35
3.5. Matching Network …………………………………………………………..36
3.5.1. Microstrip Matching Network ………………………………………38
References
4. Design of LNA …………………………………………................................39
4.1. LNA Specification ……………………………………………………….….39
4.2. Transistor Selection …………………………………………………………40
4.3. Transistor Characteristics ………………………………………………..….40
4.4. Transistor Models Comparison ……………………………………………..41
4.5. Transistor Biasing Network Design …………………………………….…..43
4.5.1. Fixed-bias Configuration …………………………………………....43
4.5.2. Self-bias Configuration ……………………………………………..43
4.5.3. Active-bias Network …………………………………………….…..44
4.6. Microstrip Footprint ………………………………………………………...44
4.7. VIA Hole Model ………………………………………………………….....45
4.8. Broadband Chip Capacitors Selection ………………………………………46 4.9. ADS Capacitor Model ………………………………………...………...…..48 4.10. DC Blocking and Decoupling ………………………………………………50
4.10.1. DC Blocking Capacitor Selection …………………………………..50
4.10.2. Dcoupling Capacitor Selection ……………………………..……….51
4.11. Microstrip RF Choke ………………………………………………………..52
4.11.1. RF Choke Design and Simulation …………………………………..52
4.11.2. RF Choke with Bias Arrangement ………………………………….54
4.12. LNA Design …………………………………………………………….…..55
4.12.1. Matching Network Design at 8.5 GHz …………………………..….59
4.12.1.1. Matching Network by Lumped Elements ……………….….60
4.12.1.2. Microstrip Matching network ………………………….……61
4.12.2. Matching Network Design at 9 GHz …………………………..……62
4.12.2.1. IMN Design …………………………………………………64
4.12.2.2. OMN Design ………………………………………………..66
4.12.3. Layout of RF Choke …………………………………………….…..70
References
5. LNA Implementation: Simulation Results and Measurements ……...72
x
5.1. Simulation Results …………………………………………………..………72
5.1.1. VIA Model Simulation ………………………………………...……72
5.1.2. DC Blocking Capacitor Simulation ……………………...………….74
5.1.3. RF Choke …………………………………………………..………..75
5.1.4. LNA with Matching Network at 8.5 GHz …………………………..77
5.1.5. LNA with Matching Network at 9 GHz …………………….………82
5.1.6. Comparison of Two LNA ……………………………………….…..83
5.1.7. LNA Layout ……………………………………………….………..85
5.2. Measurement ………………………………………………………………..87
5.3. LNA Post-manufactured Simulation ……………………………………….89
6. Conclusion and Further Work ……………………………….………….....92
Appendix …………………………………………………………………...……..93
1
1 Introduction
This chapter is intended to give an overall idea of this Master Thesis work.
The report starts with describing the background and is continues by explaining
the purpose, task and outline.
1.1 Background
Most of the today’s radio systems operate within 1 to 40 GHz which is a
part of the microwave spectrum defined by Radio Society of Great Britain [1].
Ultra-wideband radio (UWB) is a wireless communication technology based on
either orthogonal frequency division multiplexing (OFDM) or spread spectrum
technologies [2]. The UWB spectrum in the range 3.1 GHz to 10.6 GHz is defined
by the Federal Communication commission (FCC) in USA [3]. Europe, Japan and
recently China have put restriction on 3.1 to 4.8 GHz frequency band that causes
problems regarding from the coexistence of the UWB system with other
narrowband wireless system [4]. Consequently, here is a great interest in the
higher part of the UWB European Spectrum 6-9 GHz (6-8.5 GHz long term range
and 8.5-9 GHz short term range) applications [5].
Howerever, at high frequency and over a wide frequency band, it is a
challenging task to design radio receiver circuits [4]. A simple receiver front-end
consists of a Low-Noise Amplifier (LNA), filter and mixer. All active and passive
components contribute to process the signal but also they can degrade the original
signal. At each circuit, the signal must be handled carefully over a wide frequency
band to meet the design specifications [6].
For example, as the operation frequency increases above 1 GHz, the
lumped element models as those used in SPICE and SPICE-like simulators are no
longer valid. In order to provide accurate models, new design techniques based on
electromagnetic simulations should be considered. To support the new challenges,
electronic design automation (EDA) and computer aided design (CAD) vendors
have continuously improved their tools so that the entire design from system
simulation to every circuit design can be performed under a single simulation
environment [6]. Despite design difficulties, the UWB technology is considered
to be one of the promising technologies to design indoor data communication for
high data rates [4].
1.2 Purpose
The purpose of this Master thesis is to design and implement a 6-9 GHz
Low-Noise Amplifier (LNA) and to understand the design process of the LNA
module from schematic to the LNA module layout and prototype. Another
purpose is to acquire skills using the Advanced Design System (ADS) tool from
Agilent Technologies, a complex and important software for any engineer
developing circuits and systems operating at high frequencies.
2
1.3 Task
The main task was the design of a broadband 6-9 GHz LNA with the help
of ADS. At first, special theoretical knowledge about designing RF circuits was
needed. The necessary information sources were various books, scientific papers,
internet sources and useful discussions with the supervisor. The advanced ADS
skills were step-by-step learned by working and trying to solve different
problems. This thesis work also involves the passive component selection, layout
design, simulation techniques, and understanding of high frequency effects when
implementing the LNA in a PCB process.
1.4 Outline
The report is organized with six chapters including the introduction. And
the report is ended with appendix. Chapter two starts with the theoretical concepts of the UWB and radio
frequency (RF) passive components. This chapter also gives same RF
theory that was used in this work.
Chapter three covers the theoretical design consideration for the LNA.
Chapter four gives the overall design process of the LNA. This starts with
design specification then covers the component selection to matching
network design.
Chapter five contains the final LNA simulation and measurement results.
In the same time other necessary simulation results for component
selection are given.
Chapter six is for the conclusion and further work.
1.5 References
[1] Wikipedia, http://en.wikipedia.org/wiki/Ku_band.
[2] Eric Ottosson, Design and Implementation of a Ultra wide-band low noise
amplifier 3.1-4.8 GHz, Thesis LITH-ITN-ED-EX-06/017-SE.
[3] Federal Communication commission (FCC), Revision of part 15 of the
Commission’s Rules Regarding Ultra Wideband Transmission Systems,
First Report and Order ET Docket 98-153, Feb. 2002.
[4] Adriana Serban, Ultra-Wideband Low-Noise Amplifier and Six-Port
Transceiver for High Speed Data Transmission. LiU-Tryck Linkoping,
Sweden, 2010.
[5] Radio Spectrum Committee, RSCOMO7-23 Final CEPT Report on UWB
Mandate, March 2007.
http://circa.europa.eu/Public/irc/infso/Home/main?index.
[6] Adriana Serban Craciunescu, Low-Noise Amplifier Design for Ultra-
Wideband Systems, Thesis LiU-TEK-LIC-2006:62.
3
2 Ultra-wideband and General RF Theory
The main purpose of this chapter is to describe UWB and general RF
theory which are necessary for this diploma work. It is assumed that the reader
has basic knowledge of electrical engineering. The motivated reader, who would
like to get deeper understanding, can see the books and articles listed in the
references.
2.1 Ultra-wideband
Ultra-wideband (UWB) communication technology promises a huge
opportunity to impact the future communication world. Large available
bandwidth, the wide scope of the data rate/range trade-off, and low-cost operation
which will lead to massive usages, all present a unique opportunity for UWB
systems to impact the way people and intelligent machines communicate and
interact with their environment. In particularly, UWB will give huge advantages
for short-range communications. In the past 20 years, UWB has been used for
different areas e.g. radar, sensing, military communications [1]. Even though the
development and advancement of UWB system is not faster as other wireless
system, UWB will be the next best technology for all types of wireless systems
[2].
2.1.1 History of UWB
UWB history is generally perceived to start after 1960 with the
development of Linear Time Invariant System description via impulse stimuli. On
the contrary, UWB transmissions history is much older and goes back to the end
of XIX century. The history of wireless communications can be considered to
start at the end of XIX century with the work carried by Guglielmo Marconi.
From the end of XIX century until nowadays, three eras can be devised in
the history of development of UWB systems development: pioneering era (1886-
1906), subnanosecond era (1939-1994) contemporary standardization and
commercialization era (1998-2007) [3].
Despite its renewed interest during the past decade, UWB has a history as
long as radio. When invented by Guglielmo Marconi more than a century ago,
radio communications utilized enormous bandwidth as information was conveyed
using spark-gap transmitters [4]. Until 1960s communications were dominated by
continuous wave radio transmissions [3]. The next milestone of UWB technology
came in the late 1960s, when the high sensitivity to scatterers and low power
consumption motivated the introduction of UWB radar systems [4]. During the
1980s, UWB technology was referred alternately to as impulse, carrier-free or
baseband. The term ‘‘UltraWideBand’’ was first coined by the U.S. Department
of Defense in 1989. After the great technical developments, related to
subnanosecond pulses in the years from the sixties until the end of the century,
another rush started with the world-wide activities for technology standardization.
Nowadays, Multi Carrier UWB (MC-UWB), Orthogonal Frequency Division
Multiplexing (OFDM) UWB and Frequency Modulation UWB (FM-UWB) are
the strongest candidates for future UWB communication systems [3].
4
2.1.2 Theory
When UWB technology was proposed for civilian applications, there were
no definitions for the signal. According to the FCC definition, the signal is
characterized as UWB if the signal bandwidth (BW) is 500 MHz or more or a
fractional bandwidth Bf of more than 20% [5]. The fractional bandwidth is
defined as
LH
LH
c
fff
ff
f
BWB
+
−== 2 (2.1)
Where fL is the lower and fL is the higher -10 dB emission point, respectively. As
for an example, Universal mobile Telecommunication system (UMTS) operates
around 2 GHz with a bandwidth of 5 MHz. This system is often called wideband,
however according to Equation (2.1), the fractional bandwidth of UMTS is
0.0025, which is much smaller than 0.2 (i.e., 80 times smaller)!
Channel capacity of a communication system is defined by the Shannon’s
capacity theorem. The channel capacity (C bit/s) of a system relates to the
following equation.
( )SNRBWC +⋅= 1log2 (2.2)
Where signal to noise ratio, N
SSNR =
Where S is the signal power and N is the noise power respectively. It can be seen
that channel capacity increases linearly with the bandwidth (BW) and
logarithmically with SNR. So channel bandwidth is the main route to get the high
data rate.
UWB wireless personal area network (WPAN) physical (PHY) layer
standard divides the whole available ultra wideband spectrum between 3.1- 10.6
GHz into 14 sub-bands belonged to 6 band groups as show in Fig. 1 [1]. Band
group 1 is mandatory, remaining groups are optional.
Figure 2- 1 Diagram of band allocation [7]
FCC Mask
To avoid interference with existing communication systems, various
regions of the spectrum should have different allowed power spectral densities
(PSD). FCC has assigned the effective isotropic radiated power (EIRP) allowed
for each frequency band [6]. EIRP is the equivalent isotropically radiated power
5
which is the power radiated by an omnidirectional antenna with gain 1. The level
of –41.3 dBm/MHz in the frequency range of 3.1–10.6 GHz is set to limit the
interference to existing communication systems, and to protect the existing radio
services [8]. Figure 2- 2 and Figure 2- 3 shows the FCC emission limit for
outdoor and indoor UWB communications respectively. These figures also called
FCC mask.
Table 1 FCC emission limits for indoor and outdoor UWB
Frequency Ranges Indoor EIRP
(dBm/MHz)
Outdoor EIRP
(dBm/MHz)
960 MHz-1.61 GHz -75.3 -75.3
1.61 GHz-1.99 GHz -53.3 -63.3
1.99 GHz-3.1 GHz -51.3 -61.3
3.1 GHz-10.6 GHz -41.3 -41.3
Above 10.6 GHz -51.3 -51.3
Figure 2- 2 FCC emission limit for outdoor UWB communications [3]
Figure 2- 3 FCC emission limit for indoor UWB communications [3]
6
2.1.3 Regulations
One of the important issues in UWB communication is the frequency of
operation. There are many systems operating under allocated bands in the UWB
signal band. So existing narrowband allocated services to be protected from
possible interference generated in UWB systems. Figure 2- 4 shows the possible
interferes for the UWB system. It can be seen that UWB has huge bandwidth and
less PSD, whereas other narrow-band e.g. GSM, GPS, WiMAX have high PSD
and less data rate.
Figure 2- 4 Spectrum of the Main Interfering Communication Standards for UWB
Communication System [11]
In USA, the FCC committee is responsible for all kind of regulations and
legal requirements of UWB system. FCC has given permission to design and
operation of low power UWB system within 3.1 to 10.6 GHz frequency spectrum
[5].
In Europe there are number of key organizations are recognize by the
European Commission (EC). Currently ETSI, ECC and EC have all
recommended and approved the use of UWB devices within 6-8.5 GHz subject to
mitigate the technical problems arise by the FCC in USA [9].
And the extended range 8.5 to 9 GHz band which is same as US but this
band is considered for UWB impact analysis on surveillance radars. Furthermore,
EC has allowed to operate in EU 4.2 – 4.8 GHz band with -41.3 dBm/MHz and
the maximum peak EIRP of 0 dBm measured in 50 MHz [6].
2.1.4 Applications
UWB technology was first used in the Second World War by US Army
for their communication system. Since the signal at any particular frequency is
incomplete, the enemies could not able to intercept the entire message [6]. Thus
far the UWB technology has been mainly applied to military (especially radar)
appliances [9]. UWB has a number of features which make it attractive for
consumer communications applications. In particular, UWB systems
• have potentially low complexity and low cost;
• have a noise-like signal spectrum;
• are resistant to severe multipath and jamming;
7
• have very good time-domain resolution allowing for location and tracking
applications
Even with the significant power restrictions, UWB holds enormous potential for
wireless ad-hoc and peer-to-peer networks [1]. Some of the commercial
applications of UWB are given below [3]:
• Adhoc Networking e.g. WPANs
• Wireless sensor networks e.g. smart highway
• Radio Frequency Identification or RFID e.g. tag, barcode
• Consumer Electronics e.g. wireless DVD player
• Asset Location e.g. inventory items
• Medical applications e.g. medical imaging
2.2 RF Passive Components
The RF passive and active components do not behave according to simple
mathematical models; they have size, shape and are manufactured using non ideal
materials [12]. Capacitors at certain frequencies may not be capacitors at all, but
may look inductive, while inductors may look like capacitors, and resistors may
tend to be a little of both. In this chapter we will discuss about RF passive
components. But, first we will look the simplest components of any system and
examine its problem at radio frequency [13].
2.2.1 Wires
Wires used in an RF circuit can take many forms. Wire-wound resistors,
inductors, and axial- and radial-leaded capacitors all use a wire of some size and
length either in their leads, or in the actual body of the component, or both. Wires
are also used in many interconnect applications in the lower RF spectrum. The
behavior of a wire in the RF spectrum depends to a large extent on the wire’s
diameter and length [13].
Wires at low frequencies, utilizes its entire cross-sectional area as a
transport medium for charge carriers. As the frequency is increased, an increased
magnetic field at the center of the conductor presents an impedance to the charge
carriers, thus decreasing the current density at the center of the conductor and
increasing the current density around its perimeter. This increased current density
near the edge of the conductor is known as skin effect. It occurs in all conductors
including resistor leads, capacitor leads, and inductor leads. The depth into the
conductor at which the charge-carrier current density falls to l/e, or 37% of its
value along the surface, is known as the skin depth and is a function of the
frequency and the permeability and conductivity of the medium. The net result of
skin effect is an effective decrease in the cross-sectional area of the conductor
and, therefore, a net increase in the ac resistance of the wire as shown in Figure 2-
5 [13]. For copper, the skin depth is approximately 0.65 µm at 10 GHz [14].
In the medium surrounding any current-carrying conductor, there exists a
magnetic field. If the current in the conductor is an alternating current, this
magnetic field is alternately expanding and contracting and, thus, producing a
voltage on the wire which opposes any change in current flow. This opposition to
change is called self-inductance and we call anything that possesses this quality
8
an inductor. Straight-wire inductance might seem trivial, but the higher the
frequency is the more important this effect becomes. The inductance of a straight
wire depends on both its length and its diameter [13].
Figure 2- 5 Skin depth area of a wire [13].
2.2.2 Resistors
Resistors are used everywhere in circuits, as transistor bias networks, pads
etc. Behaviors of high frequency resistors are different from the world of direct
current (dc). There are different types of resistors such as carbon composite, wire-
wound, metal film and thin-film chip resistors [15]. Of these types, mainly the
thin-film chip resistors are found application in RF and MW circuits as surface
mount devices (SMDs). The electric equivalent circuit of a high frequency
resistor’s R is more complicated and parasitic components have to be considered.
Figure 2- 6 represents the equivalent circuit of a RF resistor. The model includes
two inductances L, modeling the inductor’s leads, the stray capacitance Ca and
inter-lead capacitance Cb [15].
Figure 2- 6 Electric equivalent circuit representation of the resistor [15].
Figure 2- 7 represents the example of 500 ohm thin-film resistor as a
function of frequency. This example underscores the care that is required when
dealing with RF resistors. Not all resistors behave as shown in the figure, often
multiple resonance point occurs when the frequency reaches GHz range [15].
Figure 2- 7 Absolute impedance value of a 500 ohm thin-film resistor as a function of
frequency [15].
9
2.2.3 Capacitor
A capacitor typically consists of two conducting surfaces or plates
separated by dielectric insulation material that permits the storage of energy in the
electric field between the plates. The dielectric is usually ceramic, air, paper,
mica, plastic, film, glass, or oil. Dielectric prevents current flow when applied
voltage is constant, but a time-varying voltage produces a current proportional to
the rate of voltage change [16]. The current in a capacitor is given by
dt
dvCI = (2.3)
where C is the capacitance measured in farads (F). One farad is the capacitance
that will store one coulomb of electrical charge (6.28×1018
electrons) at an
electrical potential of one volt. Or, in math form:
volts
coulombsfarads
V
QC = (2.4)
The capacitance of the parallel plate structure is given by
d
A
d
AC roεεε == (2.5)
Where
ε = absolute permittivity of the dielectric = εoεr
A = area of parallel plates
d = spacing of plates
εo= permittivity of free space
εr = relative permittivity or dielectric constant of dielectric medium
There are widespread applications of chip capacitors in the RF circuits for
the tuning and matching networks as well as for biasing active components such
as transistors. At high frequency dielectric becomes lossy. The impedance of a
capacitor must be written as a parallel combination of conductance Ge and
susceptance ωC:
CjGZ
e ω+=
1 (2.6)
Figure 2- 8 represents the equivalent circuit for a high frequency capacitor
with parasitic lead inductance L, series resistor Rs describing losses in the lead
conductors and dielectric loss resistance [15]
e
eG
R1
= (2.7)
Figure 2- 8 Electric equivalent circuit for a high frequency capacitor [15].
10
In the Figure 2- 9, the capacitor reveals a similar resonance behavior due
to the presence of dielectric losses and finite lead wires [15].
Figure 2- 9 Absolute value of the capacitor impedance as a function of frequency [15].
2.2.4 Inductor
An inductor is nothing more than a wire wound or coiled in such a manner
as to increase the magnetic flux linkage between the turns of the coil. This
increased flux linkage increases the wire’s self-inductance. Inductors are used
extensively in RF design in resonant circuits, filters, radio frequency interference
(RFI)/electromagnetic interference (EMI) suppression, phase shift and delay
networks, and as RF chokes used to prevent, or at least reduce, the flow of RF
energy along a certain path [13]. Figure 2- 10 shows a RF coil [15]. It is known
from the previous discussion that the windings represent an inductance in addition
to the frequency dependent wire resistance Rd and parasitic capacitance Cd [15].
Figure 2- 10 Distributed capacitance and series resistance in the inductor coil [4].
Inductance L is a property of electrical circuits that opposes changes in the
flow of current. An inductor stores energy in a magnetic field. The unit of
inductance is the Henry (H). A Henry is the inductance that creates an
electromotive force (EMF) of one volt when the current in the inductor is
changing at a rate of one ampere per second or in math form:
t
ILV
∆
∆= (2.8)
Where
V = created EMF in volts (V)
L = inductance in henrys (H)
I = current in amperes (A)
t = time in seconds (s)
11
∆ indicates a small change in.
Several factors affect the inductance of a coil. Perhaps the most obvious
are the length, the diameter and the number of turns in the coil. Also affecting the
inductance is the nature of the core material and its cross-sectional area [17]. Well
known formula for the inductance of an air core solenoid:
l
NrL o
22µπ= (2.9)
Where
N = number of turns
L = length of the coil
r = radius of the coil core
µo = permeability in vacuum= 4π×107 H/m
The equivalent circuit model of the RF inductor is shown in Figure 2- 11
[15]. The parasitic shunt capacitance Cs and series resistance Rs represent
composite effect of distribution capacitance Cd and resistance Rd respectively.
Figure 2- 11 Equivalent circuit model of the HF inductor [15].
Figure 2- 12 Frequency response of the impedance of an RFC [15].
Figure 2- 12 shows the frequency response of the RFC impedance which
deviates from the expected behavior of an ideal inductance at high frequencies.
Frequency dependency can form complicated resonance conditions with
additional elements in an RF system [15]. The ratio of an inductor’s reactance to
its series resistance is often used as a measure of the quality of the inductor.
sR
XQ = (2.10)
The larger the ratio, the better is the inductor. This quality factor is
referred to as the Q of the inductor. If the inductor were wound with a perfect
12
conductor, its Q would be infinite and we would have a lossless inductor. Of
course, there is no perfect conductor and, thus, an inductor always has some finite
Q. At low frequencies, the Q of an inductor is very good because the only
resistance in the windings is the dc resistance of the wire-which is very small. But
as the frequency increases, skin effect and winding capacitance begin to degrade
the quality of the inductor [13].
2.3 Active Devices:
Generally Field Effect Transistors (FETs) are used in the RF and MW
systems due to high gain and low noise figure. There are different types of FETs
family e.g. junction field effect transistors (JFETs), high electron mobility
transistors (HEMTs), metal semiconductor barrier junction transistor (MESFET).
MW transistor amplifiers are always rugged, low-cost, reliable and can be
integrated in both hybrid and monolithic integrated circuits with mixer, oscillator
and related components [18]. Basic structures of FETs for high frequency
applications are discussed in these subsections.
2.3.1 JFETs
It is the most common FET. JFET has high input impedance (on the order
of 107 to 10
12 Ω) compare to BJT. Unlike BJT, a JFET has a negative temperature
coefficient so that thermally runway is not a problem. Due to robustness, the
JFET is used as a power transistor [19].
Its operation depends on control of majority carrier in a channel by
applying voltage. This voltage, control the currents by means of an electric field.
Thus JFET is a voltage controlled current source. Figure 2- 13 shows the biasing
effect of n-channel JFET, where electrons flow from the source (S), past the gate
(G), to the drain (D). If a negative voltage is applied at the gate terminal, its
negative electric field will try to pinch the electrons flow and confine it to a
smaller cross-section of the n-channel. This affects the resistance of the n-channel
and limits the current flow. Hence by varying the gate-source voltage it is
possible to control the current flow [21].
Figure 2- 13 Biasing effect of n-channel JFET [21]
13
Figure 2- 14 IV characteristic of FET [23].
This figure shows the three regions such as triode, saturation and cut-off.
When the gate voltage is zero the maximum carrier flows through the channel
from source to drain. Cut off is the off state of the FET. It needs minimum drain
to source voltage (VDS) to turn on the FET. Once the FET is biased, the drain
current (IDS) increases linearly with VDS up to saturation level at a given value of
gate-source voltage (VGS). The power amplifier is design in the triode region
whereas the LNA is designed at the saturation region.
2.3.2 GaAs MESFET
Metal semiconductor barrier junction transistor (MESFET) is similar to
FET except that junction is a metal semiconductor barrier much as is the case
Schottkey diodes [20]. GaAs MESFET is used in high performance circuits of
communications, computer, and military systems. Specific functions for MESFET
include MW power amp, oscillator, switches, and mixer [19]. Due to higher
electron mobility GaAs is used instead of Si. That, coupled with the use of a
Schottky-barrier gate with a length of only about 1 µm, allows its use as a
microwave amplifier with very good operating characteristics [16].
Figure 2- 15 GaAs MESFET [5]
2.3.3 HEMTs
HEMTs are important recent developments in microwave and millimeter-
wave transistors. These devices make use of heterojunctions for their operation.
Cut-off
14
The heterojunctions are formed between semiconductors of different
compositions and bandgaps, for example, GaAs/AlGaAs and InGaAs/InP. These
relatively new types of devices offer significant improvements for low-noise
amplifiers and microwave power amplifiers [16].
Figure 2- 16 HEMT [16]
Figure 2- 16 shows the cross-section of an HEMT structure using GaAs
and AlGaAs. The conventional HEMT is similar to a GaAs MESFET. As seen in
figure HEMT has two ohmic contacts (source and drain) and a Schottky gate. The
difference between the two types of devices and the key to the HEMT’s improved
performance is in the underlying semiconductor material. The HEMT has superior
electron transport properties and much higher sheet charge density than the
MESFET because of a two-dimension electron gas layer that is formed in a thin
layer between the AlGaAs and the undoped GaAs layers.
HEMPTs have demonstrated unprecedented noise performance at
cryogenic temperatures (within a few degrees of absolute zero) and good
microwave and millimeter-wave noise and power performance at room
temperature at frequencies up to 60 GHz. Typical noise figures at 12 GHz for
commercially available low-noise HEMTs are about 1.0 dB In addition to lower
noise figure, HEMTs also have several characteristics that make them more
attractive for low-noise applications. They are easier to provide impedance
matching, and they have a larger gain-bandwidth product [16].
2.3.4 FET Transistor Modeling
FET Transistor is nonlinear device and for circuits analysis different types
of models are used e.g. small signal, large signal. Moreover these small and large
signal models are divided into low and high frequency applications. Small-signal
modeling is a common analysis technique is used to approximate the behavior of
nonlineaer devices with linear equations. This linearization is formed about the
DC bias point of the device (that is, the voltage/current levels present when no
signal is applied). Nothing changes because the assumption is that the signal is so
small that the operating point (gain, capacitance etc) doesn't change. Large-signal
modeling is a common analysis method used in electrical engineering to describe
nonlinear devices in terms of the underlying nonlinear equations. This model
takes into account the fact that the large signal actually affects the operating point
and takes into account that elements are non-linear and circuits can be limited by
power supply values.
15
2.3.4.1 High Frequency model of FET
It is necessary to take some considerations for the high frequency model
of FET. FET structure acts as a parallel capacitor when viewed from the gate and
source terminals. Frequency dependent components are: Cgs – gate to source
capacitance, Cgd -gate to drain capacitance and Cds -drain to source capacitance. Drain to source capacitance is small and less effect of high frequency.
Capacitance can be modeled as voltage dependent in the following ways [22]
m
o
GS
gso
gs
V
CC
+
=
ψ1
and m
o
GD
gdo
gd
V
CC
+
=
ψ1
where
Cgso and Cgdo are the zero bias gate-source and gate-drain junction
capacitance; VGS and VDS are the quiescent gate-source and drain-source voltage;
m is the gate p-n grading coefficient (SPICE default is 0.5) and ψo is the gate
junction (barrier) potential typically 0.6 V [22].
Figure 2- 17 High frequency FET model [22]
The maximum operating frequency ωT, is the frequency at which the FET
no longer amplifies the input signal i.e. the dependent current source gmvgs is
equal to the input current [22].
( )dsgs
mT
CC
g
+=ω (2.11)
2.4 Transmission Line
In the conventional low frequency circuit analysis the Kirchhoff’s laws
can be applied where voltages and currents are uniform all over the conductor. At
the higher frequencies the Kirchhoff’s laws can not be applied directly due to
spatial behavior of the voltage and current. A new approach is needed to explain
the transmission line which is called distributed circuit theory. The transmission
lines considered here are system of two or more parallel conductors [3]. The line
is subdivided into infinitesimal length ∆z, over which voltage and current can be
assumed to remain constant depicted in Figure 2- 18 [4].
16
Figure 2- 18 Segment of transmission line expressed with distributed parameters R, L, C and
G, where all parameters are given in terms of unit length [4].
Applying Kirchhoff’s voltage laws in the Figure 2- 18
)()()()( zVzzVzzILjR =∆++∆+ ω (2.12)
which is re-expressed as a differential equation
)()()(
zILjRdz
zdVω+=− (2.13)
Applying Kirchhoff’s current laws to the node a in Figure 2- 18 yields
)()()(
zVCjGdz
zdIω+−=− (2.14)
From equation (2.13) and (2.14) we can get the standard 2nd
order differential
equation
0)()( 2
2
2
=− zVkdz
zVd (2.15)
0)()( 2
2
2
=− zIkdz
zId (2.16)
Where k is known as a complex propagation constant
))(( CjGLjRjkkk ir ωω ++=+= (2.17)
Solutions of equation (2.15) and (2.16) are two exponential functions for the
voltage and current.
kzkzeVeVzV
+−−+ +=)( (2.18)
kzkzeIeIzI
+−−+ +=)( (2.19)
Equation (2.18) and (2.19) are the general solutions for the transmission lines
aligned along the z-axis. From these two equations, the characteristic line
impedance Z0 can be defined as
)(
)()(0
CjG
LjR
k
LjRZ
ω
ωω
+
+=
+= (2.20)
Characteristic impedance can be written as
−
−
+
+
−==I
V
I
VZ0 (2.21)
17
Z0 is not impedance in the conventional circuit sense. Its definition is based on the
positive and negative travelling voltage and current waves.
2.4.1 Lossless Transmission Line
The characteristic line impedance defined in equation 2.20 is a complex
quantity and therefore there will be losses always in the realistic lines [4]. There
are two regions where Z0 tends to be resistive and constant [9]. The first region
occurs at very low frequencies when LjR ω>> and CjG ω>> . These results in
G
RZ =0 (2.22)
The second region occurs at very high frequencies when RLj >>ω and
GCj >>ω . These result in
C
LZ =0 (2.23)
which is a constant factor and the transmission line is said to be lossless because
there are no dissipative elements in the line. Equations (2.22) and (2.23) are very
important because under these conditions the line impedance tends to remain
frequency independent and a state known as ‘distortion-less transmission’ [21].
2.4.2 Voltage Reflection Coefficient
High frequency electric circuits can be viewed as a collection of finite
transmission line sections connected to various discrete active and passive
devices. Therefore consider the terminated line of length l shown in Figure 2- 19
[4]. We know the voltage along the line is given by (2.18). The second term in
(2.18) has the meaning of a reflection from the terminating load impedance for
values z < 0. Voltage reflection coefficient 0Γ indicates the amount of reflected
wave with respect to incident wave at the load 0=z .
+
−
=ΓV
V0 (2.24)
Figure 2- 19 Terminated transmission line at location z=0.
Reflection coefficient can be written as
18
0
00
ZZ
ZZ
L
L
+
−=Γ (2.25)
which involves known circuit quantities and independent of voltage wave. For the
case where load impedance matches the line impedance i.e. LZZ =0 , no reflection
occurs and 00 =Γ .
2.4.3 Standing Wave Ratio
Standing wave ratio (SWR) is defined as the ratio of the maximum voltage
(current) over the minimum voltage (current). This is the best way to find the
mismatch of a transmission line.
min
max
min
max
I
I
V
VSWR == (2.26)
Another form of SWR is
0
0
1
1
Γ−
Γ+=SWR (2.27)
which has a range of ∞<≤ SWRl For the matched termination 1→SWR and for
the worst case of either open or short circuit results in ∞→SWR .
2.5 Microstrip Transmission Line
Microstrip line is one of the most popular types of planner transmission
lines. It is cheap to manufacture, easily integrated with passive and active devices
[8]. Geometry of microstrip line is shown in the Figure 2- 20 [4] where W is the
width of the line, d is the thickness of the dielectric and εr is the relative
permittivity of dielectric. The phase velocity and propagation constant of a
microstrip line can be expressed as
Phase velocity eff
p
cv
ε= (2.28)
Propagation constant effk εβ 0= (2.29)
where εeff is the effective dielectric constant of the microstrip line which satisfies
the relation, reff εε <<1 and is independent of on the substrate thickness d and
conductor width W.
Figure 2- 20 (a) Microstrip line; (b) end view of microstrip line [9].
19
By neglecting the thickness of the conductor, t compare to the substrate
height, d, the characteristic impedance can be represent with the line dimension
(W and d). For narrow strip line, 1/ <dW , the line impedance,
)4
8ln(2
0d
W
W
dZZ
eff
f +=επ
(2.30)
Where 8.376)/( 00 == εµfZ Ω, is the wave impedance in free the space and
the effective dielectric constant is given by
−+
+
−+
+=
− 22/1
104.01212
1
2
1
W
d
W
drreff
εεε (2.31)
For the wide line W/d > 1, line impedance is
+++
=
444.1ln3
2393.1
0
W
d
W
d
ZZ
eff
f
ε
(2.32)
With
2/1
1212
1
2
1−
+
−+
+=
W
drreff
εεε (2.33)
With the knowledge of the effective dielectric constant we can compute the
expression for the wavelength of
effeff
p
f
c
f
v
ε
λ
ελ 0=== (2.34)
where c is the speed of light and f is the operating frequency.
2.6 Transmission Line as Electrical Components
It is possible to design transmission line that will behave like electrical
components e.g. capacitor, inductor, resistor, transformer. These components are
made by careful choice of transmission line characteristic impedance (Z0), line
length (l) and termination (ZL). The properties of these components can be
calculated by using well known expressions for calculating the input impedance
of a transmission line. From the transmission line equation the voltage reflection
coefficient can be written as [1]
0
0
ZZ
ZZ
L
Lv
+
−=Γ (2.35)
20
Figure 2- 21 Line voltages reference to the load end [21]
It is more convenient to take voltage and current references from the
terminating or load end of the line. This is shown in Figure 2.6. From the
definition of line attenuation and for a distance l from the load, we have incident
and reflected voltages [21]
l
iLi eVvγ+= (2.36)
and l
rLr eVvγ+= (2.37)
And using the definition for voltage reflection coefficient Γv
l
L
il
rlvl e
V
V γ2−Γ==Γ (2.38)
where
l = line length
Γv= voltage reflection coefficient at load
Γvl= voltage reflection coefficient at load distance l from load
γ = propagation constant = α+jβ nepers/m
At any point on a transmission line of distance l from the load
l
viiril evvvvvγ2−Γ+=+= (2.39)
l
iiiril eiiiiiγ2−Γ+=+= (2.40)
Dividing Equation (2.39) by (2.40) and defining Zl at point l and Zo
Γ−
Γ+=
−
−
l
v
l
vol
e
eZZ
γ
γ
2
2
1
1 (2.41)
If the total length of the line is l, the impedance at point l becomes the input
impedance (Zin) of the line. After doing some calculation, Zin can be written as
+
+=
lZlZ
lZlZZZ
Lo
Looin
γγ
γγ
sinhcosh
coshsinh (2.42)
We know propagation constant, βαγ j+= . When the line is considered as low
loss i.e. α << β, then propagation constant becomes βγ j= . Since we know
λπβ /2= where λ is the electrical length at the frequency of operations, so
Equation (2.42) becomes
21
+
+=
λ
π
λ
πλ
π
λ
π
lZ
ljZ
lZ
ljZ
ZZ
oL
Lo
oin 2cos
2sin
2cos
2sin
(2.43)
This equation will investigate the property of transmission line.
2.6.1 Transmission Line as a Reactances
A transmission line can be made to behave like a reactance by making the
terminating load a short circuit ( 0=LZ ). In this case, Equation (2.43) becomes
λ
π
λ
πλ
π
λ
πλ
πl
jZl
lj
Zl
Z
ljZ
ZZ oo
o
o
oin
2tan
2cos
2sin
2cos0
02
sin
=
=
+
+= (2.44)
When 4/λ<l , λ
πljZZ oin
2tan= (2.45a)
is an inductive.
When 2/4/ λλ >< l , λ
πljZZ oin
2tan−= (2.45b)
is a capacitive.
Similar reactive effects can be produced by open-circuited load.
λ
πljZZ oin
2cot−= (2.46)
At the radio frequency any unterminated transmission has a stray
capacitance with an open circuit. This stray capacitance can be ignored for our
frequencies of operation, its reactance is extremely high [21].
2.6.2 Transmission Line as a Transformer:
When 2/λ=l , Equation (2.43) becomes
L
oL
Looin Z
ZjZ
ZjZZZ =
+
+=
ππ
ππ
cossin
cossin
So transmission line acts as a 1:1 transformer. A resistor dissipating a lot
of heat adjacent to a transistor can cause the latter to malfunction. With a 1:1
transformer, the resistor can be physically moved away from the transistor
without upsetting electrical operating conditions.
when 4/λ=l , Equation (2.43) becomes
L
oin
Z
ZZ
2
= (2.47)
Input impedance becomes higher when length of transmission line
becomes quarter wave. This concept can be used in the bias circuit of active
device.
22
2.7 Smith Chart
Smith chart is a very useful tool for RF circuit design e.g. amplifier,
oscillator. Gain circles, noise circles, matching network design, impedance and
admittance determination, and finding reflection coefficients and voltage standing
wave ratio can be represented using the Smith chart [21]. The Smith chart was
developed by P.H. Smith in the late 1930s. Figure 2- 22 shows a simplified Smith
chart.
Figure 2- 22 Smith Chart.
The Smith chart is a phasor diagram of the reflection coefficient, Γ, on
which constant-r and constant-x circles are drawn, where r and x are the
normalized values of the series resistive and reactive parts of the load impedance.
The horizontal and vertical axes of the chart are the real and imaginary axes of the
reflection coefficient. Any circle centered on the Smith chart centre is a constant-
|Γ| circle and a constant VSWR circle too.
The Smith chart, described so far as a family of impedance coordinates,
can easily be used to convert any impedance (Z) to an admittance (Y), and vice-
versa. In mathematical terms, an admittance is simply the inverse of an
impedance, or
ZY
1= (2.48)
where, the admittance (Y) contains both a real and an imaginary part, similar to
the impedance (Z). Thus
jBGY ±= (2.49)
G = Conductance in Siemens (S)
B = Susceptance in Siemens (S)
Open
circuit
Short
circuit
Inductive
domain
Capacitive
domain
Wavelengths
to generator
Wavelengths
to load
23
2.7.1 Smith Chart Theory
This section deals with the derivation of the resistance (R) and reactance
(X) circles of the Smith chart.
The normalized load impedance is
jxrZ
jXR
Z
Zz L +=
+==
00
(2.50)
And the reflection coefficient is
ir jΓ+Γ=Γ (2.51)
From the Equation (2.25) we can write
Γ−
Γ+=
1
1z (2.52)
Substituting z and Г in Equation (2.50)
ir
ir
j
jjxr
Γ−Γ−
Γ+Γ+=+
1
1 (2.53)
can be separated into
22
22
)1(
1
ir
irrΓ+Γ−
Γ−Γ−= (2.54)
and ir
ixΓ+Γ−
Γ=
2)1(
2 (2.55)
The Equation (2.54) and (2.55) are the transformations rules of finding z if
the reflection coefficient is specified in term of Гr and Гi. We can derive the
parametric equations of circles from (2.54) and (2.55) as
2
2
2
1
1
1
+=Γ+
+−Γ
rr
rir (2.56)
( )22
2 111
=
−Γ+−Γ
xxir (2.57)
Both (2.56) and (2.57) are parametric equations of circles in Г-plane.
Figure 2- 23 represents the parametric circle equations (2.56) for various
normalized resistances. For example, if the normalized resistance r is zero, the
circle is centered at the origin. And in the limit for ∞→r , the circles radius
approaches 0)1/( →+rr . This mapping is for fixed values of r only and does not
involve x. thus for a fixed value of r, an infinite range of reactance values x as
indicated by straight line in z-plane [15].
24
Figure 2- 23 Parametric representation of the normalized resistance r [15].
Figure 2- 24 represents the parametric circle Equations (2.57) for various
normalized reactance. Here the centers of the circles reside along a line
perpendicular to the 1=Γr point. For ∞=x , the circle of radius becomes zero. It
is observed that negative x-values refer to capacitive impedances residing in the
lower half of the Г-plane [15].
Figure 2- 24 Parametric representation of the normalized reactance x [15].
Individually equation (2.56) and (2.57) does not construct unique mapping
from normalized impedance into the reflection coefficient plane. Figure 2- 25
represents the smith chart by combining r and x circles for 1≤Γ . This Smith
chart is a one-to-one mapping between normalized impedance and the reflection
coefficient plane. It is also noticed that resistance circles r have a range ∞<≤ r0
and the reactance circles x can be either negative (capacitive) or positive
(inductive) values in the range, ∞+<∞− x . For the computation of the input
impedance of a terminated transmission line, the motion is always away from the
load impedance or towards the generator. This rotation is indicated by an arrow
on the periphery of the chart [15].
25
Figure 2- 25 Smith chart by combining r and x circles for 1≤Γ [15].
2.7.2 Smith Chart Applications
The basics of Smith chart and theory have been discussed before. Some of
the applications of Smith chart are given in this section.
a) Reflection Coefficients Evaluation
Smith chart can be used to find the reflection coefficient at any point, in
phasor form. Figure 2- 26 shows a point A (08-j1.6). The line OA is extended to B
and the resulting angle BOC is about -55.50. The modulus of the reflection can be
found from equation (2.27) which states that the voltage standing wave ratio,
v
vVSWR
Γ−
Γ+=
1
1
where Γv is the voltage reflection coefficient. VSWR is obtained by
completing the circle enclosing the point A. It is then read off the intersection
between the circle and the real axis and in this case the value is 5. So
( ) ( ) 667.015/15 =+−=Γv and hence the reflection coefficient is 05.55667.0 −∠
[21].
Figure 2- 26 Reflection coefficient: A = (0.8-j1.6), angle BOC=-55.5 degree [21].
26
b) Impedance Transformation using Smith Chart
ZY Smith chart allows impedance transformation from a given value (ZL)
to a desired value (Zin). This is done using a T-type network shown in Figure 2-
27[15]. Using the Smith chart for computation of the input impedance of this
network we have assumed 500 =Z ohm and 2=cf GHz.
Figure 2- 27 T network connected to the base-emitter input impedance of a bipolar
transistor. Assuming 500 =Z ohm and 2=cf GHz [15]
Series-shunt transitions are shown in Figure 2- 28 with the help of ADS
Smith chart tool [15].
Figure 2- 28 Computation of the normalized input impedance of the T network
2.8 Networks Model
Up to a few tens of MHz the analog circuits are characterized by
admittances, impedances, voltages, and currents. It is not possible to measure
voltage and current or impedance directly above these frequencies. It is better to
use such as voltage reflection and transmission coefficients that can be easily
measured and are related to power flow. As well, in RF and microwave (MW)
circuit design the power of signal and of noise is always of interest [24]. So for
RF and MW circuits single- and multiport network models give great advantages
for analog circuits and components to input and output port parameters
irrespective of their complicated and often nonlinear behavior. The main
ZL Zin
B
C
D
AE
27
advantage of this network model is the experimental determination of input and
output port parameters without knowing the internal structure of the system [15].
At first the basic two-port network input-output parameter relations such
as impedance, admittance, hybrid, ABCD- are discussed and shown how these
quantities can be decomposed into sum of incident and reflected waves. This
leads to the scattering matrix, which gives an alternative characterization of two-
port network in terms of incident and reflected waves. This matrix is called
scattering parameters (S-parameters) and is central to modern RF and MW circuit
design [18].
2.8.1 Two-port Networks
In the maximum circuit analysis methods require that the voltage at each
terminal referenced to a common ground, which is difficult in the RF and MW
circuits. Thus at radio frequencies ports are used, shown in Figure 2- 29. The
network in Figure 2- 29 has four terminals and two-ports. Reciprocity, symmetry,
passivity and linearity are four fundamental propertied of networks. A network is
linear if the response, voltages and currents are linearly dependent on drive level.
So if the two-port shown here is linear, the currents I1 and I2 are linear functions
of V1 and V2. A symmetrical two-port network has the same properties in each of
the ports i.e. transmission line. A reciprocal two-port has a response at port 2 from
an excitation at port 1 and vice-versa. A passive network has no internal sources
of power [24].
Figure 2- 29 Two-port network [15].
At low frequencies design the mostly used parameters are impedance,
admittance, hybrid, and chain or ABCD which relates the input and output
voltages and currents. The relationships of currents and voltages in the input-
output port can determine by combination of either short- or open-circuiting the
ports. The voltage at each port is given by
2211111 IZIZV += (2.58)
2221212 IZIZV += (2.59)
Or in a matrix form the impedance parameters are
=
2
1
2221
1211
2
1
I
I
ZZ
ZZ
V
V (2.60)
Admittance or Y-matrix form:
=
2
1
2221
1211
2
1
V
V
YY
YY
I
I (2.61)
28
Hybrid or h-matrix form:
=
2
2
1
1
I
V
CD
AB
I
V (2.62)
Chain or ABCD- matrix form:
=
2
1
2221
1211
2
1
V
I
hh
hh
I
V (2.63)
ABCD parameters are the best parameters for cascading two ports, when
total voltage and current relationships are required [24]. The hybrid parameters
h21 and h12 define the forward current and reverse voltage gain respectively and
remaining two determine the input impedance (h11) and out put admittance (h22).
So the hybrid parameters are used for low frequency transistor models [15].
2.8.2 S-parameters
Measurements of Z, Y, h and ABCD parameters require the ports be
terminated in either open or short circuits that could result in undesired behavior,
including oscillation or destruction to the device under test (DUT). Moreover in
RF and MW it is difficult to realize a good open and short condition. Since RF
circuits are designed with close attention to maximum power transfer conditions
and resistive load (i.e. 50 Ω), as these are close to the actual operating conditions
and so the effect of measurement errors will have less compare to imperfect opens
and shorts [24]. So in the RF and MW frequency domain S-parameters are used
to characterize the two-port network [15]. S-parameters are related to power flow
and permits to define the input-output relations of a network in terms of incident
and reflected power waves. With reference to Figure 2- 30, a generic two-port
network is driven from a source with impedance usually equal to 500 =Z Ω and
driving a load of impedance ZL [21].
Figure 2- 30 Two port scattering network with source and load [21]
As seen in above figure the incident normalized power wave an and a
reflected normalized power wave bn are defined as follows:
( )nnn IZVZ
a 0
02
1+= (2.64)
( )nnn IZVZ
b 0
02
1−= (2.65)
Where n refers either to port 1or 2 and Z0 is the characteristic impedance of the
connecting lines on the input and output side of the network. The four waves (a1,
29
a2, b1 and b2) are related by the following equations where S11, S12, S21 and S22 are
the S-parameters:
2121111 aSaSb += (2.66)
And
2221212 aSaSb += (2.67)
Equations (2.50) and (2.51) can be written in matrix form as
=
2
1
2221
1211
2
1
a
a
SS
SS
b
b (2.68)
where S11 and S22 are the input and output reflection coefficient
respectively and whereas other S21 and S12 are the forward and backward voltage
gain respectively.
References
[1] Maria-Gabriella Di Benedetto, Thomas Kaiser, Andreas F. Molisch, Ian
Oppermann, Christian Politano, and Domenico Porcino, UWB
Communication Systems A Comprehensive Overview. Hindawi, USA,
2006.
[2] Jim Geier, A Technology to Consider: Ultra-wideband, February 25,
2003. www.wi-fiplanet.com/tutorials/article.php/1598581
[3] Homayoun Nikookar and Ramjee Prasad, Introduction to Ultra Wideband
for Wireless Communications. Springer, USA, 2009.
[4] Liuqing Yang and Georgios B. Giannakis, Ultra-wideband
communications - An idea whose time has come. IEEE signal Processing
Magazine, November 2004.
[5] Federal Communication commission (FCC), Revision of part 15 of the
Commission’s Rules Regarding Ultra Wideband Transmission Systems,
First Report and Order ET Docket 98-153, Feb. 2002.
[6] Magnus Karlsson, Ultra-wideband Antenna and Radio Front-end System.
PhD thesis, Linkoping University, Sweden, 2007.
[7] “High Rate Ultra Wideband PHY and MAC Standard,” Standard ECMA
368, 2nd Edition, Dec. 2007
[8] S. Hongson et al., ‘‘On the spectral and power requirements for UWB
transmission,’’ ICC 2003, vol. 1, May 2003, pp. 738–742.
[9] D. Taylor, Ultra Wideband Radar Technology. CRC Press, USA, 2001.
[10] Radio Spectrum Committee, RSCOMO7-23 Final CEPT Report on UWB
Mandate, March 2007.
http://circa.europa.eu/Public/irc/infso/Home/main?index.
[11] Peng Wang, Fredrik jonsson, Hannu Tenhunen, dian Zhou, Li-Rong
Zheng, “Low Noise Amplifier Architecture Analysis for OFDM-UWB
System in 0.18µm CMOS”. 26th
Norchip Conference 2008. Page(s):184-
189, IEEE 2008.
[12] Gary Breed, “Fundamentals of Passive Component Behavior at High
Frequencies”, High Frequency Electronics, June 2006, Summit Technical
Media.
30
[13] Chris Bowick, RF Circuit Design. Howard Sams & Co., Indianapolis, IN,
1982.
[14] Wikipedia, http://en.wikipedia.org/wiki/Skin_effect.
[15] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall Inc, USA, 2000.
[16] Ferril Losee, RF Systems, Components and Circuits Handbook. Artech
House, USA, 1997
[17] Joseph J. Carr, RF Components and Circuits. Radio Society of Great
Britain, UK, 2002.
[18] David M. Pozar, Microwave and RF Design of Wireless System. John
Wiley & Sons, USA, 2001.
[19] Kwok K. NG, Complete guide to Semiconductor Devices. Wiley-
Interscience, Canada, 2002.
[20] Savant, Roden and carpenter, Electronic Design Circuits and Systems. The
Benjamin/Cummings publishing, USA, 1987.
[21] E. da Silva, High Frequency and Microwave Engineering. Butterworth-
Heineman, 2001.
[22] Ernie Kim, Class Lecture EEE 194 Section 4: RF & Microwave
Engineering, University of Sandiego. http://home.sandiego.edu/~ekim
[23] W.Marshall Leach, Class Lecture ECE3050 Analog electronocs. Georgia
Institute of Technology. http://users.ece.gatech.edu/mleach
[24] Michael Steer, Microwave and RF Design A system Approach. Scitech,
USA, 2009
31
3 Low-Noise Amplifier
Low-noise amplifier (LNA) is the first active gain stage of any radio
receiver where amplification is always a critical function. Moreover, for the ultra-
wide band (UWB) systems, the LNA becomes more challenging because of wide
frequency range, low noise figure (NF), high gain and low power consumption
[1]. Virtually all MW and RF amplifiers use three terminal solid state devices
such as junction field effect transistors (JFETs), high electron mobility transistors
(HEMTs) and hetero junction bipolar transistors (HBTs). MW transistor
amplifiers are always rugged, low-cost, reliable and can be integrated in both
hybrid and monolithic integrated circuits with mixer, oscillator and related
components [2]. As details of receiver are beyond the scope of this thesis work
and only a short theory is described in the following subsection, for a better
understanding of the LNA design.
Designing a LNA for UWB applications implies minimizing the NF and
maximizing the power gain and avoiding the undesirable oscillation and
appropriate matching to reduce the voltage standing wave ratio (VSWR). For
these reasons stability is the first step for the LNA design [3].
3.1 Receiver Overview
Receiver is at the heart of all communication systems. The basic function
of the receiver is to distinguish the signal from noise irrespective of how simple
or complex the system is. Here, the signal is some form of modulated
electromagnetic wave and the noise is like to be a random signal either from man-
made or natural [4]. There are different types of receiver architectures that are
used depending on applications e.g. heterodyne, homodyne and super-heterodyne.
Each of this architecture has its own pros and cons.
RF receiver using a heterodyne architecture is shown in Figure 3- 1, where
some of the circuitries are enclosed by dotted line as a frond-end of the receiver.
The main needs of the receiver front-end are amplification, mixing, filtering and
demodulation. It can be observed that the front-end includes three bandpass filters
(BPFs). The BPF1 right after the antenna is used to select the band of interest of
received signal and referred to as a band selection filter. Since the desired signal
at the receiver antenna is very low (some microvolts), so the signal needs
amplification. This amplification must be done with minimum additional noise
injected by the amplifier itself, using low-noise amplifier (LNA) [5].
Figure 3- 1 RF receiver using a heterodyne architecture [5].
32
The amplification is followed by mixing, and the mixer should be
continued by anti-image filter (BPF2). In this approach a mixer with variable
local oscillator (LO) is followed by a fixed bandpass filter (BPF3). BPF3 operates
at intermediate frequency (IF) and quality factor of this filter is assumed relax.
The BPF3 is also called channel filter. The channel filter is followed by an IF
amplifier to improve the signal. The demodulator takes this output and performs
demodulation [5].
3.2 Stability
Stability is one of the major concerns of an amplifier circuit within the
frequency of interest. An RF circuit tends to oscillate depending on frequency and
terminations of source and load [3]. The stability of LNA could be defined by
Rollett factor k as
12
1
2112
22
22
2
11 >∆+−−
=SS
SSk (3.1)
where
21122211 SSSS −=∆ (3.2)
If k >1 and ∆<1 then the amplifier remains stable condition throughout the
entire domain of the Smith chart at the selected frequency and bias conditions.
One way is to stabilize an active device is to add a shunt conductance or series
resistance either at input or output port. For a LNA it is good option to avoid
resistive elements at the input port since they cause additional noise to be
amplified. But stabilization through addition of resistors comes at a prize such as
gain, noise and matching [3].
3.3 Noise Analysis
Noise limits the performance of all receivers. There are two types of noise
sources-internal where the noise is generated by the receiver itself and external
where noise is received by the antenna. External noise sources include both
natural and man-made sources. Industrial noise, signals from radar or
communication transmitter that provide interference and jamming sources are
man-made noises. Natural noise sources are lightning storms, solar noise and
atmospheric-loss noise. At VHF and higher frequencies, internally generated
noises are generally greater than external noises received by the antenna and
therefore are the limiting factor in system performance [6].
3.3.1 Internal Noise Sources
As long as the internal noise is the limiting factor at the higher frequency,
we will discuss common noises generated by the electronic devices. Some of the
noise sources are given below:
• Thermal noise
It is also known as a Nyquist or Johnson noise. This is caused by the
random motion of charge carriers. This type of noise generated in any passive
33
elements that contains loss such as resistor, base and emitter resistance of bipolar
transistor, channel resistance of MOSFETs (Figure 3- 2). Due to the noise the root
mean square (RMS) value of voltage fluctuation across a resistor is defined as [7]
kTBRVn 4= (3.3)
where
k = Boltzmann’s constant
T = Absolute temperature (0K)
B = Bandwidth (Hz)
R = Resistance (Ohm)
Figure 3- 2 Thermal noise [7]
• Shot Noise
Shot noise is associated with the current flow across a potential barrier. It
is due to the fluctuation of current from the random emission of electrons (or
holes). In the semiconductors, the shot noise is due to random diffusion of carriers
through the base of a transistor and the random generation and recombination of
hole electron pairs [7].
qIBIn 22 = (3.4)
where
q = electron charge
I = average current
B = noise bandwidth
Figure 3- 3 Shot noise [7]
• Flicker Noise
Flicker noise arises from random trapping of charge at the oxide- silicon
interface of MOSFETs. This noise is represented as a voltage source in series
with the gate as [7]
fWLC
KV
ox
n
12 = (3.5)
where
34
K = Process-dependent constant
W = Width of channel
L = Length of channel
Cox = Oxide capacitance per unit length
f = Frequency
As the noise is inversely proportional to frequency so the effect of this
noise is negligible at higher frequencies. With these noise sources, a two port
system can be modeled by two input noise generators: a series voltage source and
a parallel current source (Figure 3- 4) [7].
Figure 3- 4 Representation of noise by input noise generators [7].
3.3.2 Noise Figure
Most of the front-end receiver is characterized by the noise figure. Noise
figure (NF) is defined as
out
in
SNR
SNRNF = (3.6)
where SNRin and SNRout are the signal-to-noise power ratios measured at the input
and output respectively. Noise figure is a measure of how much the SNR
degrades. If a system has no noise then outin SNRSNR = , regardless of the gain.
The noise figure of LNA in a receiver chain can be found form the Friis equation
as
( )12121
3
1
21
....
1......
1111
−
−++
−+
−+−+=
i
mtot
GGG
NF
GG
NF
G
NFNFNF (3.7)
where Gi and NFm represent the gain and noise of each stage. From this
equation it is clear that the total noise figure is dominated by the first stage, NF1
i.e. the noise of the LNA. At the same time the gain of the first stage, G1 reduces
the noise contribution in the subsequent circuits [8]. Sensitivity of an RF receiver
is defined as the minimum signal level that the system can detect with acceptable
signal-to-noise ratio. Sensitivity of a system can be defined as
minmin. log10/174 SNRBNFHzdBmPin +++−= (3.8)
where -174 dBm/Hz represents the noise power that source delivers to the
receiver at room temperature considering conjugate matching at the receiver
input. Sum of the first three terms is called “noise floor” [7].
35
3.4 Power Gain
Different power gain definitions are used to understand the RF amplifier
functions. Besides the stability and noise, gain is also a concern for LNA design.
In order to define the power gain, a simplified single stage amplifier is shown in
Figure 3- 5 [3].
Figure 3- 5 Simplified single stage amplifier [3]
Input and output reflection coefficients of the above figure can be expressed as
L
Lin
S
SSS
Γ−
Γ+=Γ
22
122111
1 (3.9)
S
Sout
S
SSS
Γ−
Γ+=Γ
11
122122
1 (3.10)
• Available Power Gain
Power launched towards the amplifier is defined as
2
2
12
1
Sin
S
inc
bP
ΓΓ−= (3.11)
where bs is the source voltage and can write as
s
s
s VZZ
Zb
0
0
+= (3.12)
Input reflection has to consider for the actual input power Pin of the amplifier.
( )21 inincin PP Γ−= (3.13)
Maximum power transfer from the source to the amplifier is achieved
when the amplifier is properly conjugated matched or in terms of reflection
coefficients, if *
Sin Γ=Γ . Under this condition the gain is called available gain, PA
as
2
2
12
1
S
S
A
bP
Γ−= (3.14)
• Transducer Power Gain
Transducer gain, GT is defined as the ratio of the power delivered to the
load to the available power from the source. This is the actual gain of an amplifier
36
stage including the effects of input and output matching and device gain [9].This
gain quantifies the gain of the amplifier placed between source and load [3].
A
LT
P
PG = (3.15)
Where PL is the power delivered to the load and
( )22
2 12
1LL bP Γ−= (3.16)
So after several calculations the transducer gain can be written as
( ) ( )( )( ) 2
12212211
22
21
2
11
11
SLLS
SL
TSSSS
SG
ΓΓ−Γ−Γ−
Γ−Γ−= (3.17)
• Operating Power Gain
Operating power gain, GP is defined as the ratio of the power delivered to
the load to the power supplied to the amplifier.
in
AT
in
LP
P
PG
P
PG == (3.18)
• Maximum Available Gain (MAG)
The maximum gain can be found from a transistor under a conjugately
matched condition is called maximum available gain (MAG). This can be
calculated by two steps [9]:
1. Calculate the intermediate quantity called B1 where
22
22
2
111 1 ∆−−+= SSB (3.20)
∆ is calculated from Equation 3.2.
2. Calculate MAG using the result from Equation 3.1
1log10log10 2
12
21 −±+= kkS
SMAG (3.21)
Here the value of MAG in dB and k must be greater than 1
(unconditionally stable). Polarity B1 determines which sign (+or -) to use before
the radical Equation (3.21). If the value of MAG for a particular transistor i.e. 15
dB and the design called for a minimum gain greater than 15 dB, a different
transistor would be needed [9].
3.5 Matching Network
After selection of a transistor or gain block for a particular design, there is
not much can be done within the active device other than present efficient ways in
which energy can be coupled in and out of the device. This is called efficient
matching circuits for the intended purposes [9]. In order to achieve maximum
37
power transfer, we need to match the impedance of the load to that of the source
and this is done usually by putting additional passive networks between load and
source [3]. This networks are called matching network. In the RF circuits this
networks is also used for minimizing the noise, linearizing the frequency response
and maximize power handling capabilities. In other way matching network could
be defined as a transformation of given impedance to more suitable value [3].
The cheapest and most reliable matching networks are the two
components networks. Due to the arrangement of components, this is also called
L-sections network. Figure 3- 6 [3] shows the eight possible combinations of
elements connected in series and shunt configuration. This network consists of
one capacitor and one inductor. Using the Smith chart tool, initially we can easily
design this network.
Figure 3- 6 Eight possible two components networks [3].
Figure 3- 7 [3] shows the impedance effect of L and C combinations. The
general thumb rule is that whenever an inductor is involved, we rotate towards the
upper half of the Smith chart and a capacitor results in the movements towards the
lower half.
Figure 3- 7 Impedance effects of series and shunt connections of L and C [3].
38
3.5.1 Microstrip Matching Network
In order to meet the performance of a wideband LNA, it is critical to
design the proper matching networks. Du to the parasitic effect at the higher
frequency, the discrete lumped elements are not suitable and distributed element
is a good alternative. Multi section microstrip matching networks can be used for
the UWB LNA design [10]. Details of the input and output matching network
with microstrip elements are give in Chapter Four.
3.6 References
[1] Peng Wang, Fredrik jonsson, Hannu Tenhunen, dian Zhou, Li-Rong
Zheng, “Low Noise Amplifier Architecture Analysis for OFDM-UWB
System in 0.18µm CMOS”. 26th
Norchip Conference 2008. Page(s):184-
189, IEEE 2008.
[2] David M. Pozar, Microwave and RF Design of Wireless System. John
Wiley & Sons, USA, 2001.
[3] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall, USA, 2000.
[4] Josep J. Carr, RF Components and circuits. Newnes, UK, 2002.
[5] Bosco Leung, VLSI for Wireless Communication. Prentice Hall, USA,
2002.
[6] Ferril Losee, RF Systems Components and Circuits Handbook. Artech
House, USA, 2005.
[7] Behzad Razavi, RF Microelectronics. Prentice Hall, USA, 1998.
[8] Adriana Serban Craciunescu, Low-Noise Amplifier for Ultra-Wideband
System. LiU-TEK-LIC-2006:62
[9] E. da Silva, High Frequency and Microwave Engineering. Butterworth-
Heineman, 2001.
[10] Adriana Serban and Shaofang Gong, Ultra-Wideband Low-Noise
Amplifier Design for 3.1-4.8 GHz. GigaHertz 2005.
39
4 LNA Design
Throughout the LNA design, we have used the ADS design tool from the
Agilent Technologies. We can divide the entire design into two steps i.e. schematic
level design and layout level design. Schematic level design includes schematic
capture, choosing a simulation type (DC, S-parameters, etc.) and choosing the
simulation set-up. Once the schematic is verified through simulation, it can be used
as a component or sub-network in another ADS design.
Once the LNA design was optimized on schematic level, different
components are converted into their layout representation: microstrip input and
output matching networks, bias network including pads for different lumped
components. Finally the RF module layout is designed. Simulations are performed
with Momentum, which is an electromagnetic simulator in ADS. It computes the S-
parameters for any planer topology including microstrip, vias and multi layer
structures. Using Momentum properties and parasitic coupling between components
are included in the of the RF circuit. One powerful possibility of the ADS is the
possibility of producing “layout components” which can be individually optimized
and further used.
4.1 LNA Specification
LNA specifications are taken from the requirements of the radio front-end
receiver in the ultra-wideband applications. There is no certain bandwidth spectrum
for the UWB all over the world. Different regions and countries have their own
bandwidth. In Europe and Asia, 6-9 GHz bandwidth is preferred in order to avoid
radio interference with other system [1]. The designed LNA must satisfy the
following specifications.
Operating frequency range 6-9 GHz
Noise figure below 2 dB
Output gain above 10 dB
Table 2 shows the substrate properties of the designed LNA. One important point of
substrate property is that for the simulation, dielectric constant value is different from
the actual value [2].
Table 2 Rogers RO4350B, substrate property [2]
RO4350B
Substrate property Typical value
Dielectric constant εr 3.48±0.05 mm
3.66 (for Simulation)
Dielectric thickness 0.254 mm
Metal thickness 0.035 mm
Metal conductivity 5.8e7 S/m
Copper roughness 0.001 mm
Dissipation factor 0.0037 mm
40
4.2 Transistor selection
Selection of a proper transistor defines the whole performances of the LNA.
There are different families of FET. We need such a transistor which will meet the
required specifications. NE3512S02 Hetero-Junction Field Effect Transistor is used
for this work which covers the 6-9 GHz bandwidth with reasonable gain and noise.
According to the data sheet of NE3512S02, Figure 4- 1 shows the minimum noise
figure and power gain within the required bandwidth [3].
Figure 4- 1 Minimum noise figure, associated gain vs. frequency characteristics [3].
4.3 Transistor Characteristics
In order to design a LNA we need to choose a proper bias point. Figure 4- 2
shows the ADS simulation setup for the I-V characteristic of the transistor using the
electrical model of NE3512S02. The simulation result is shown in the Figure 4- 3
which coincides with the data sheet result in Figure 4- 4 [2].
Source
Drain
Gate
VAR
VAR1
VGS =0 V
VDS =0 V
EqnVar
ParamSweep
Sweep1
Step=0.1
Stop=0
Start=-0.6
SimInstanceName[6]=
SimInstanceName[5]=
SimInstanceName[4]=
SimInstanceName[3]=
SimInstanceName[2]=
SimInstanceName[1]="DC1"
SweepVar="VGS"
PARAMETER SWEEP
I_Probe
IDS
V_DC
SRC2
Vdc=VGS
V_DC
SRC1
Vdc=VDS
DisplayTemplate
disptemp3
"FET_curve_tracer"
TempDisp
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
DC
DC1
Step=0.01
Stop=2.5
Start=0
SweepVar="VDS"
DC
NEC_FET
Q1
partName=NE3512S02_v118
Figure 4- 2 ADS Simulation setup for the I-V characteristic using electrical model of
NE3512S02.
41
0.5 1.0 1.5 2.00.0 2.5
0
10
20
30
-10
40
VGS=-0.600VGS=-0.557VGS=-0.514VGS=-0.471VGS=-0.429VGS=-0.386VGS=-0.343VGS=-0.300VGS=-0.257VGS=-0.214
VGS=-0.171VGS=-0.129VGS=-0.086VGS=-0.043VGS=0.000
Drain to Source Voltage VDS (V)
Dra
in C
urr
en
t ID
(m
A)
m1
Figure 4- 3 Simulated I-V Characteristic of NE3512S02.
Figure 4- 4 I-V Characteristic of NE3512S02 according to data sheet [3]
For the proper biasing of the designed LNA we have chosen mAID 20= ,
VVGS 17.0−= and VVDS 2= . Marker (m1) in the Figure 4- 3 shows the biasing point
of the LNA.
4.4 Transistor Models Comparison
At high frequency it is necessary to use proper transistor models which will
meet the reliable circuit operation. Two types of models are used for the circuit
design e.g. lumped models (which can be small-signal or large-signal models) and S-
parameter models, either as data sets resulting from simulations or from
measurements.
Lumped elements models are based on the physical properties of the transistor
such as oxide thickness, substrate doping concentration etc. In the low and medium
frequency these models give the accurate information about the circuit. The S-
parameter models of the active devices, i.e. transistor are used to evaluate stability,
power gain, noise-figure and bandwidth both in the conceptual stage of the circuit
design and during the circuit design using CAD-tools.
42
S- Parameter ModelElectrical Model
S2P
SNP1
Type=Touchstone
File="NE3512S02v2_2-18_2_20.s2p"
21
RefTerm
Term3
Z=50 Ohm
Num=3
Term
Term4
Z=50 Ohm
Num=4
Term
Term2
Z=50 Ohm
Num=2
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
S_Param
SP1
Step=0.1 GHz
Stop=18 GHz
Start=2 GHz
S-PARAMETERS
VAR
VAR4
VGG=-0.17
EqnVar
VAR
VAR3
VDD=2
EqnVar
DisplayTemplate
disptemp1
"S_21_11_wZoom"
"S_Params_Quad_dB_Smith"
TempDisp
NEC_FET
Q1
partName=NE3512S02_v118
V_DC
SRC2
Vdc=VGG V
DC_Block
DC_Block2
V_DC
SRC1
Vdc=VDD V
I_Probe
IDS
DC_Feed
DC_Feed1
DC_Block
DC_Block1
Term
Term1
Z=50 Ohm
Num=1
DC_Feed
DC_Feed2
Figure 4- 5 Simulation setup for the Electrical and S-Parameter model of NE3512S02.
The S-parameter model is suitable for high frequency applications [4] Figure
4- 5 shows the ADS simulation setup for the simulation of S-parameters of the
transistor using the two models. The simulation results are show in the Figure 4- 6.
From these results, we can conclude that the small-signal model is enough accurate to
be used when necessary. However, we can see that the S-parameters resulting from
these two models do not coincide. We also know that at high frequency, the
measured S-parameters model is better to be used that the lumped model. Along this
project we have mainly used the S-parameter model for the transistor.
freq (2.000GHz to 18.00GHz)
S(1
,1)
S(3
,3)
freq (2.000GHz to 18.00GHz)
S(2
,2)
S(4
,4)
freq (2.000GHz to 18.00GHz)
S(2
,1)
S(4
,3)
Input Reflection Coefficient Output Reflection Coefficient
Forward Voltage Gain Reverse Voltage Gain
freq (2.000GHz to 18.00GHz)
S(1
,2)
S(3
,4)
Figure 4- 6 S-Parameters are estimated using Electrical (Thick line) and S-Parameter model
(Thin line) at the Q-point (ID = 20 mA and VDS = 2 V).
43
4.5 Transistor Biasing Network Design
The purpose of a good dc bias design is to select the proper quiescent point
and hold the quiescent constant over the variation of transistor parameters and
temperature [5]. There are at least three ways to bias up a FET amplifier to get the
intended quiescent point. These are
4.5.1 Fixed-bias Configuration
The simplest of biasing arrangement for the FET is fixed-bias configuration
which is shown in Figure 4- 7. It has separate DC power supplies for the Gate and
Drain connections and ground the source. Grounding the source directly will provide
the most gain from the FET and this is a good concept if efficiency is a concern [7].
In order to prevent transient burn-out of the GaAs FET device during turn-on, the
gate voltage must be applied before drain voltage. If the drain is biased positive
before the gate, then transistor will operate momentarily beyond its safe operating
region. This type of configuration is suitable for low noise, high gain, high power and
high efficiency applications [6]. This bias network is used for the LNA design.
Figure 4- 7 Fixed-bias Configuration [7]
4.5.2 Self-bias Configuration
Self-bias network eliminates the need of two dc supplies. Figure 4- 8[7]
shows the self-bias configuration. A resistor of a strategic value is placed between the
source connection and ground. The resistor is bypassed with a capacitor so that the
FET source connection sees a zero Ω connection to ground at the operating
frequency. When drain current flows through the FET and then through the source
resistor, the source voltage rises above ground. The gate voltage is either held at a
fixed voltage or grounded, resulting in a fixed negative gate-source voltage. The
main disadvantages of this scheme are that amplifier efficiency is lost due to the
voltage drop of the source resistor. Also, the FET cannot be RF grounded at all
frequencies as well as if it was DC grounded with via holes, so gain and efficiency
can be degraded as a result. Self-bias networks are often used in LNA, but not power
amplifiers, for these two reasons [7].
44
VDDID
Vi
VGS-
+
Vo
R
R4
R=RD
L
L2
R
R3
R=RG
L
L1
C
C3
C
C1 NEC_FET
Q2
R
R5
R=RS
C
C2
Figure 4- 8 Self-bias Configuration [7]
4.5.3 Active-bias Network
Active bias network (Shown in Figure 4- 9) is another method of biasing a
FET. This type of network is usually preferred for large temperature change. Figure
4- 9 [8] shows the Active current mirror using a negative bias to supply a negative
voltage to the FET. The circuit keeps the drain current constant regardless to the
value of gm in the FET which falls over life and would under fixed bias cause the
drain current to fall [8].
-Vee
Vo
Vds
Vi
+Vcc
+
-VGS
R
R7
R=R3
R
R11
R=R2
R
R10
R=R1
R
R9
R=Rd
BJT_PNP
BJT1
NEC_FET
Q3
Figure 4- 9 Active-bias Configuration [8].
4.6 Microstrip Foot-print
It is known that each microstrip component plays an important role in the RF
system design especially for the LNA design which is the vital part of the radio front-
end system. In ADS, the library component model use SMT pad for generating the
proper footprint in the layout level. But there are no effects in simulation with SMT
pad in the schematic level. So it is necessary to make layout component of foot-print
for individual component. The layout component of foot-print will add parasitic
effect in the SMT component model simulation and provides accurate result close to
real life component. Different layout components of foot-prints are generated using
ADS tool. At first a layout foot-print is design according to standard foot-print
specification. Then ADS Momentum simulation is performed for each foot-print.
Finally layout component of individual footprint is generated.
45
NEC_FET_foot
NEC_FET_foot_1
TL6
TL5TL4
TL7
Z0805
Z0805_1
Z0603
Z0603_1
Z0402
Z0402_1
Figure 4- 10 Layout component of footprint for the transistor (NE3512S02) and three types of
packages such as 0402, 0603 and 0805.
Figure 4- 10 shows the different layout component for the active and passive
components. All dimensions are specified according the given data sheet values.
4.7 Via Hole Model
We can not achieve ideal ground for the real-life circuit. There is always
some impedance in the ground. It is common practice to have RF ground through via.
The VIA must be closed to the component terminal. According to the ADS model
(Figure 4- 11(h)), via hole is considered as a cylindrical conductor that will add
additional inductance in the ground path [9]. Especially for the transistor’s common-
source grounding through via, we need to reduce inductance in the source terminal.
So if we can put multiple vias closely together then overall inductance will be less
than a single via. Layout component model of via could better option for accurate
simulations. Using the same way of foot-print layout generation, different layout
components of via models were designed as shown in Figure 4- 11 .
(h) ADS via model(0.4 mm) (g) One 0.2 mm via(f) One 0.4 mm via with 1.6 mm microstrip line
(c) Six 0.4 mm via(b) Three 0.4 mm via(a) One 0.4 mm via (d) One 0.4 mm via with 5 mm microstrip line
(e) Two 0.4 mm via with 5 mm microstrip line
Z11
Z11_1
ModelType=MW
VIA2
V1
T=0.00375 mm
H=0.254 mm
D=0.4 mmZ14
Z14_1
ModelType=MW
Z16
Z16_1
ModelType=MW
Z15
Z15_1
ModelType=MW
Z12
Z12_2
ModelType=MW
K17
K17_1
ModelType=MW
Z08
Z08_1
ModelType=MW
Figure 4- 11 Different layout components of via hole model and ADS via model.
Simulation results of the layout via models are presented in Figure 4- 13.
These simulation results show that multiple (Figure 4- 13 (c) six 0.4 mm) via model
provides less reflection coefficient i.e. better grounding comparing to other models.
46
(c) Six 0.4 mm via
(b) Three 0.4 mm via
(a) One 0.4 mm via
Term
Term6
Z=50 Ohm
Num=6
Term
Term1
Z=50 Ohm
Num=1
Term
Term3
Z=50 Ohm
Num=3
Term
Term4
Z=50 Ohm
Num=4
Term
Term2
Z=50 Ohm
Num=2
Z08
Z08_2
ModelType=MW
K17
K17_2
ModelType=MW
Z12
Z12_1
ModelType=MW
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
S_Param
SP1
Step=0.1 GHz
Stop=18 GHz
Start=0 GHz
S-PARAMETERS
DisplayTemplate
disptemp1
"S_Params_Quad_dB_Smith"
TempDisp
Term
Term5
Z=50 Ohm
Num=5
Figure 4- 12 ADS set-up for via simulation.
m2freq=S(3,3)=0.981 / 171.026impedance = Z0 * (0.010 + j0.078)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(3
,3)
m2
m2freq=S(3,3)=0.981 / 171.026impedance = Z0 * (0.010 + j0.078)
9.000GHzm1freq=S(1,1)=0.971 / 167.769impedance = Z0 * (0.015 + j0.107)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(1
,1)
m1
m1freq=S(1,1)=0.971 / 167.769impedance = Z0 * (0.015 + j0.107)
9.000GHz
(a) (b)
m3freq=S(5,5)=0.987 / 173.531impedance = Z0 * (0.006 + j0.057)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(5
,5)
m3
m3freq=S(5,5)=0.987 / 173.531impedance = Z0 * (0.006 + j0.057)
9.000GHz
(c)
Figure 4- 13 Reflection coefficients for different via models.
4.8 Broadband Chip Capacitor Selection
General description of the capacitor is given in the RF passive components
section. Selection criteria of chip capacitors for the RF broadband applications e.g.
bypassing FET source, DC blocking and coupling are discussed in this subsection. In
order to get the proper chip capacitor for the design, it is necessary to consider the
overall performances of the circuit. Typical requirements for selecting a chip
capacitor for the wireless applications are [10]:
• Capacitance (pF)
• Tolerance (%)
• Equivalent series resistance (ESR)
• Series resonant frequency(Fsr)
• Parallel resonant frequency(Fpr)
• Temperature coefficient(TC, PPM/0C)
• Tolerance (%)
• Voltage Rating (WVDDC, VRMS)
47
• Equivalent Series Resistance (ESR)
An ideal capacitor stores all of its energy in the dielectric, as 2
2
1CV . It is
known from previous discussion that a real capacitor always shows series resistance.
This resistance is called equivalent series resistance (ESR). ESR contributes mainly
dielectric and metal losses of a capacitor. These losses at the higher frequencies
become more significant because of skin effect and increase proportionally as the
square root of frequency. We can calculate the ESR value at the desired frequency
from the specified frequency byspecified
desiredspecifieddesired
f
fESRESR = . The power loss of a
capacitor is ESRIP2= [10].
• Quality Factor (Q)
This is a figure of merit and is a measure of a capacitor’s ability to store
energy. SinceESR
XQ c= , low ESR yields high Q. As with ESR, the Q must be
specified at the design frequency [10].
• Dissipation Factor (DF)
This is also referred to as the loss tangent is the reciprocal of Q. the tangent of
the loss is equal to the dissipation factor and indicates what portion of the total
reactive power in the capacitor will be lost as heat i.e. dissipation loss.
anglelossDF _tanθ= .
• Series Resonant Frequency (Fsr)
Capacitor’s series resonance frequency also referred to as self-resonance. At
this frequency the capacitor’s net reactance is zero and the impedance is equal to
ESR. Figure 4- 14 shows the comparison of a 100 pF ATC capacitor model with the
ideal capacitor. Marker indicate the series resonance frequency, Fsr and provide
lowest impedance path making it an ideal coupling element at 1 GHz. Net impedance
below the Fsr is capacitive and above the Fsr is inductive[11].
48
1 2 30 4
2
4
6
8
10
12
0
14
Frequency (GHz)
Imp
ed
an
ce
(O
hm
)
m1
Figure 4- 14 Impedance vs Frequency. Solid line represents for ATC100A101 (100pF) and dot
line for ideal 100 pF capacitor [11] .
• Parallel Resonant Frequency (Fpr)
Figure 4- 15 shows the insertion loss of ATC100A101 (100 pF) capacitor.
Parallel resonance frequency is observed as a sharp attenuation in the S21 magnitude
in the Figure 4- 15. It is important to see one or more parallel resonant falling within
the operating passband. If a parallel resonance does fall within the operating band it
will be necessary to evaluate its depth in order to determine whether or not the loss is
acceptable. An insertion loss of several tenths of a dB is generally acceptable
criterion for most coupling applications.
2 4 6 8 10 12 14 160 18
-50
-40
-30
-20
-10
-60
0
Frequency (GHz)
Ma
gn
itu
de
dB
(S(2
1))
Figure 4- 15 Insertion loss (S21) of ATC100A101 (100 pF) capacitor [11].
4.9 ADS Capacitor Model
Selecting a capacitor is a big issue for broadband applications like in UWB
LNA design. There are several physical models of SMT capacitors in ADS library
component. The SMT capacitor represents an equivalent circuit model embedded
within the netlist of the schematic design and different companies use unique model
for their components. Using different model gives different results. Moreover
component availability was another issue for the LNA implementation. Since
capacitors from the Kemet manufacturer were available, so it is good to use Kemet
49
SMT capacitor model for the LNA design. Some of the capacitors models are given
below.
• Kemet Ceramic SMT Capacitor Model
Figure 4- 16 Kemet COG ceramic capacitor model schematic [12].
Figure 4- 17 Kemet X7R ceramic capacitor model schematic [12].
• Murata Monolithic ceramic SMT Capacitor Model
Figure 4- 18 Murata Monolithic ceramic SMT Capacitor model [12].
• ATC SMT Capacitor Model
Figure 4- 19 CAPP2 (Chip capacitor) model for ATC [12].
• Philips Measurement-Based CMC Capacitor Model
This capacitor model is different from the other model. This capacitor is not
represented by an equivalent circuit like other models. This capacitor is based on
actual frequency dependent S-parameter files [12].
50
From above SMT capacitor models it is clear that overall frequency responses
will vary from each other. Figure 4- 20 shows an example of 1 pF capacitor’s
property for varies SMT capacitor models. The insertion losses are not same for all
models.
2 4 6 8 10 12 14 160 18
-30
-20
-10
0
-40
10
Frequency (GHz)
Fo
rwa
rd T
ran
sm
issio
n (
dB
)
ATC
Murata
Philips
Kemet
Figure 4- 20 Forward transmission vs frequency characteristics for 1 pF capacitor dofferent
companies such as Kemet, ATC, Philips and Murata.
4.10 DC Blocking and Decoupling
In the microwave amplifier design, RF signal coexist with the DC signal
which gives power to the active device. So it is necessary to separate these two types
of signal for the proper circuit operation. Refereeing to Figure 4- 7, DC blocking
capacitor Ci and Co are simple capacitors that have a low series reactance at the RF
frequency and act like an open circuit for the DC signal. Decoupling capacitor, C will
suppress the power supply noise. RF choke L will allow the DC signal for biasing the
active device. In the same time RF choke will prevent the RF signal to mix with DC
signal. At the higher frequency ideal RF choke will not give the proper bandwidth
and microstrip quarter-wave transmission lines are better solution [13]. Microstrip RF
choke will discuss in later.
4.10.1 DC Blocking Capacitor Selection
Impedance and forward transmission behaviors of Kemet capacitor model for
different values are shown in Figure 4- 21. Solid line shows sharp insertion loss in
the lower band. So Kemet 10 pF capacitor model could be used for the DC blocking
purpose in the RF input and output port.
51
2 4 6 8 10 12 14 160 18
-25
-20
-15
-10
-5
-30
0
Frequency (GHz)
Fo
rwa
rd T
ran
sm
issio
n (
dB
)
1 pF
2.7 pF
10 pF
Figure 4- 21 Forward Transmission vs Frequency characteristic of Kemet capacitor model with
different values.
4.10.2 Decoupling Capacitor Selection
Broadband bypassing is a critical design matter that needs careful attention.
Multiple capacitor approach gives more efficient solution for wider frequency
spectrum [11]. In this design there are four decoupling capacitors C1 through C4 are
chosen to obtain low impedance path to ground. C1 will suppress in-band 6-9 GHz
carrier frequency from appearing on the DC supply and its Fsr is close to amplifier s
operating frequency. And C2 through C4 capacitor will suppress the RF energy at the
frequency below the operating frequency. Figure 4- 22 shows the forward
transmission behavior for the C1 through C4 decoupling capacitors. Four different
capacitor values are 10 pF, 100 pF, 220 pF and 100 nF respectively.
2 4 6 8 10 12 14 160 18
-30
-20
-10
-40
0
Frequency (GHz)
Fo
rwa
rd T
ransm
issio
n (
dB
)
C1C2
C3
C4
Figure 4- 22 Forward Transmission vs Frequency for Bypassing Kemet capacitor model. Thick
line for C1 and thin line for C2 to C4
52
4.11 Microstrip RF Choke
Figure 4- 23 shows the microstrip RF choke that consists of three parts such
as quarter wavelength transformer (L1), open circuited stub (L2) and an arbitrary
length (L3). Open circuited stub could be made by different microstrip elements.
Third butterfly stub is used to design the RF choke which gives broader bandwidth
compare to microstrip stub.
Figure 4- 23 Three types of RF choke [13].
Theoretically a RF choke provides a low loss RF path from port1 to port2 and
an infinite impedance towards port 3 i.e. DC bias port. At the centre frequency open-
circuited (L2) stub provides RF short at point B. The quarter wavelength transmission
line (L1) transforms the RF short at point B to RF open i.e. infinite impedance at
junction point A [13].
4.11.1 RF Choke Design and Simulation
The simulation setup of the three type’s microstrip RF choke is given below.
The simulation results of forward transmission between port one and two are given in
Figure 4- 27. From these simulation results it is clear that butterfly RF choke gives
wider bandwidth than others chokes. Transmission line width (W) is 0.524 mm is
defined by 50 Ω at 7.5 GHz, quarter wave length (L1) is 5.22 mm at 8.5 GHz and
radial angle is 78 degree is used throughout the design.
53
Term
Term1
Z=50 Ohm
Num=1
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
S_Param
SP1
Step=0.1 GHz
Stop=12 GHz
Start=0 GHz
S-PARAMETERS
MLOC
TL298
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee34
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Term
Term2
Z=50 Ohm
Num=2
Term
Term3
Z=50 Ohm
Num=3MLIN
TL289
L=5 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL295
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL296
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Figure 4- 24 ADS set-up for RF choke using quarter wave stub.
Term
Term2
Z=50 Ohm
Num=2
MRSTUB
Stub3
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
Term
Term1
Z=50 Ohm
Num=1
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
S_Param
SP1
Step=0.1 GHz
Stop=12 GHz
Start=0 GHz
S-PARAMETERS Term
Term3
Z=50 Ohm
Num=3
MLIN
TL289
L=5 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee34
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL295
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL296
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Figure 4- 25 RF choke using radial stub.
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Term
Term1
Z=50 Ohm
Num=1
Term
Term2
Z=50 Ohm
Num=2
S_Param
SP1
Step=0.1 GHz
Stop=12 GHz
Start=0 GHz
S-PARAMETERS
MRSTUB
Stub4
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL296
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL295
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
MRSTUB
Stub3
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
Term
Term3
Z=50 Ohm
Num=3
MCROSO
Cros1
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL289
L=5 mm
W=0.524 mm
Subst="MSub1"
Figure 4- 26 RF choke using butterfly stub.
But in the practical circuit the DC line (port 3) is not 50 Ω terminated. But for
butterfly RF choke there is less effect on termination at port3. Butterfly choke is
simulated with different values such as 5 Ω, 10 Ω, 20 Ω, and 50 Ω termination at the
port 3 and simulation results are given in Figure 4- 28.
54
Figure 4- 27 Forward transmission vs frequency characteristics of different types of RF chokes
(Thick line for Butterfly, Thin line for quarter wave line and Das line for radial).
2 4 6 8 100 12
-15
-10
-5
-20
0
Frequency GHz
Forw
ard
Tra
nsm
issio
n d
B(S
(2,1
))
Figure 4- 28 Forward transmission vs frequency with different terminated values in port 3 (Das
line for 5 ohm, star line for 10 ohm thin line for 20 ohm and thick line for 50 ohm).
4.11.2 RF Choke with Bias Arrangement
After seeing the termination condition at port 3 (DC line), it was necessary to
see the parasitic effects of capacitor in this RF choke. So all bypass capacitors with
their footprint layouts are added and simulated. Figure 4- 29 shows the complete
schematic of RF choke with bypass capacitor arrangement. The impedance at port 3
is more close to RF short than a 50 Ω (Port 1 and 2). Among the three types of RF
choke, the butterfly stub is most robust with any termination at port 3 [13]. Figure 4-
30 shows the optimized simulation results. RF choke gives good forward
transmission between port 1 and 2 and high impedance towards port 3. This RF
choke has designed at the higher band frequency (8.5 GHz) instead of center
frequency (7.5 GHz)
2 4 6 8 100 12
-15
-10
-5
-20
0
Frequency GHz
Forw
ard
Tra
nsm
issio
n d
B(S
(2,1
))
Stub
Radial stub
Butterfly stub
55
Term
Term3
Z=50 Ohm
Num=3
Term
Term2
Z=50 Ohm
Num=2
Term
Term1
Z=50 Ohm
Num=1
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MCROSO
Cros1
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee31
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL291
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL290
L=2 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee29
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee30
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL292
L=2 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee32
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL288
L=2 mm
W=0.524 mm
Subst="MSub1"
Z0805
Z0805_1
ModelType=MW
sc_kmt_X7R_08055_M_19960828
C27
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART_NUM=C0805C104M5R 100nF
sc_kmt_C0G_06035_J_19960828
C25
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_D_19960828
C24
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
MLIN
TL289
L=2 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL296
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL295
L=1 mm
W=0.524 mm
Subst="MSub1"
MRSTUB
Stub3
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
SMT_Pad
Pad2
PO=-0.23 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.457 mm
W=1.22 mm
SMT_Pad
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
S_Param
SP1
Step=0.1 GHz
Stop=12 GHz
Start=1 GHz
S-PARAMETERS
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
MRSTUB
Stub2
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
Z0603
Z0603_4
ModelType=MW
Z0603
Z0603_5
ModelType=MW
Z0603
Z0603_2
ModelType=MW
Z0603
Z0603_3
ModelType=MW
Figure 4- 29 Complete Schematic of RF choke with bias arrangement.
2 3 4 5 6 7 8 9 10 111 12
-20
-15
-10
-5
-25
0
Frequency GHz
Fo
rwa
rd T
ran
sm
iss
ion
dB
(S(2
,1))
2 3 4 5 6 7 8 9 10 111 12
-90
-80
-70
-60
-50
-40
-30
-100
-20
Frequency GHz
Fo
rwa
rd T
ran
sm
iss
ion
dB
(S(3
,1))
(a) (b)
Figure 4- 30 Forward transmission vs frequency characteristic for the schematic of Figure 4- 29.
4.12 LNA design
Primarily S-parameter model of selected transistor (NE3512S02) is going to
use throughout the LNA. After getting the LNA layout with proper input and output
matching network, we will use lumped elements model of the transistor. Using the
fixed-bias network, the transistor’s operating bias point is already adjusted in the
previous section as 20=DI mA, 17.0−=GSV V and 2=DSV V. It is needed to see
the Rollett factor or stability factor of the model either stable or unstable within the
operating frequency. From the simulation result it is clear that it is necessary to
increase the stability factor within the operating frequency. So stabilization
techniques are used to get stable operation within the bandwidth (6-9 GHz). Figure 4-
56
33(a) and (b) shows the gain and noise figure (star line) respectively before
stabilization.
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
VAR
VAR1
Z0=50
EqnVar
MeasEqn
meas1Eqn
Meas
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=4 GHz
S-PARAMETERSS2P
SNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
RefTerm
Term1
Z=Z0
Num=1
Term
Term2
Z=Z0
Num=2
Figure 4- 31 Schematic of the NE3512S02 S-parameter model before stabilization.
5 6 7 8 94 10
0.5
1.0
1.5
0.0
2.0
Frequency GHz
Sta
bili
ty F
acto
r K
Figure 4- 32 Stability factor vs frequency before stabilization.
5 6 7 8 94 10
12
14
16
18
10
20
Frequency GHz
Po
we
r G
ain
dB
(S(2
,1))
5 6 7 8 94 10
0.4
0.6
0.8
0.2
1.0
Frequency GHz
No
ise
Fig
ure
dB
(a) (b)
Figure 4- 33 Power gain and noise figure before stabilization.
The transistor is stabilized by adding a series resistor at the output. Figure 4- 34
shows the DC annotation after stabilize the transistor.
Minimum noise figure
Actual noise figure
57
-170 mV -170 mV 2.05 V2.05 V
2.13 V
3.00 V
1.06 uV-85.0 nV
-85.0 nV -170 mV 2.05 V 2.13 V 1.06 uV
-170 mV
-170 mV
2.13 V
3 V3 V
-170 mV
-170 mV
-170 mV
-170 mV -170 mV
-170 mV
-170 mV
-170 mV -170 mV 2.13 V 2.13 V
2.13 V
2.13 V
2.13 V 2.13 V
3.00 V
3.00 V
DC
DC1
Step=0.1
Stop=3
Start=0
SweepVar="VDS"
DC
20.3 mA
-20.3 mA
-25.2 pA
NEC_FET
Q1partName=NE3512S02_v118
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=4 GHz
S-PARAMETERS
20.3 mA
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="Pad1"
PART _NUM=RC-I-0603-43R0-G 43 Ohm
20.0 aA
Z0603
Z0603_2
ModelType=MW
20.0 aA
Z0603
Z0603_4
ModelType=MW
20.0 aA
Z0603
Z0603_5
ModelType=MW
-1.13 aA
Z0603
Z0603_8
ModelT ype=MW
-1.13 aA
Z0603
Z0603_6
ModelT ype=MW
-1.13 aA
Z0603
Z0603_7ModelT ype=MW
-20.3 mAZ25_Mline
Z25_Mline_1
ModelType=MW
14.2 aA
Z0603
Z0603_12
ModelType=MW
21.3 nAZ25_Mline
Z25_Mline_3
ModelT ype=MW
1.70 nAZ25_Mline
Z25_Mline_2
ModelType=MW
0 A
Z0603
Z0603_1
ModelType=MW
VAR
VAR4
VGS=-0.17
VDS=3
EqnVar
-1.70 nA
sc_kmt_C0G_06035_D_19960828
C36
SMT _Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
21.3 nAT erm
T erm2
Z=Z0
Num=2
-1.70 nAT erm
T erm1
Z=Z0
Num=1
-21.3 nA
sc_kmt_C0G_06035_D_19960828
C37
SMT _Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
-1.73 nA
sr_ims_RC-I_0603_G_19950814
R3
SMT _Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
11.3 aA
Z0402
Z0402_1
ModelType=MW
zzzzzzzz
zzzzzzzz_1
ModelType=MW
-1.14 aA
Z0603
Z0603_11
ModelType=MW
-3.59 aA
Z0805
Z0805_2
ModelT ype=MW
30.0 nAsc_kmt_C0G_06035_D_19960828C24
SMT_Pad="Pad1"
T emperature=25
PART _NUM=C0603C100D5G 10pF
20.1 aA
Z0603
Z0603_10
ModelType=MW
-20.3 mA
sr_ims_RC-I_0603_G_19950814
R1
SMT _Pad="Pad1"
PART_NUM=RC-I-0603-3R90-G 3.9 Ohm
SMT_Pad
Pad2
PO=-0.23 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.457 mmW=1.22 mm
SMT_Pad
SMT_Pad
Pad1
PO=-0.15 mmSM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
-20.3 mA
V_DC
SRC1
Vdc=VDS V
20.3 mA I_Probe
IDS
8.53 nA
V_DC
SRC2
Vdc=VGS V
MeasEqn
meas1EqnMeasVAR
VAR1
Z0=50
EqnVar
Options
Options1
T nom=25
T emp=16.85
OPTIONS
-1.70 nA
sc_kmt_C0G_06035_D_19960828
C28
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
-1.70 nA
sc_kmt_X7R_08055_M_19960828
C31
SMT_Pad="Pad2"
T emperature=25
Vtest=1
PART _NUM=C0805C104M5R 100nF
-1.70 nA
sc_kmt_C0G_06035_J_19960828
C30
SMT _Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
-1.70 nA
sc_kmt_C0G_06035_J_19960828
C29
SMT_Pad="Pad1"
T emperature=25
PART _NUM=C0603C101J5G 100pF
0 A
-1.73 nA
-114 fA
1.73 nA
MCROSO
Cros2
W4=0.524 mm
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
25.0 pA
-1.73 nA
1.70 nA
MT EE_ADS
Tee34
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
T echInclude_NEC_ACTIVELIBRARY
NEC_ACT IVELIBRARY_Lib
File=Nominal
1.73 nA
MLIN
TL304
L=5.22 mm
W=0.524 mm
Subst="MSub1"
-6.83 nA
1.70 nA
5.13 nA
MTEE_ADS
Tee38
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
5.13 nA
MLIN
TL303
L=2 mm
W=0.524 mm
Subst="MSub1"
3.43 nA
MLIN
TL302
L=2 mm
W=0.524 mmSubst="MSub1"
-3.43 nA
1.70 nA
1.73 nA
MTEE_ADS
Tee37
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
-5.13 nA
1.70 nA
3.43 nA
MTEE_ADS
Tee36
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
6.83 nA
MLINTL301
L=2 mm
W=0.524 mm
Subst="MSub1"
-8.53 nA
1.70 nA
6.83 nA
MTEE_ADS
Tee35
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
-1.73 nA
MLIN
TL300
L=2 mm
W=0.524 mm
Subst="MSub1"
8.53 nA
MLIN
TL299
L=2 mm
W=0.524 mm
Subst="MSub1"
-25.2 pAMLIN
TL298
L=1 mm
W=0.524 mm
Subst="MSub1"
1.70 nAMLIN
T L297
L=1 mm
W=0.524 mm
Subst="MSub1"
-15.1 fA
MRSTUB
Stub5
Angle=78L=4 mm
Wi=0.524 mm
Subst="MSub1"
-15.1 fA
MRSTUB
Stub4
Angle=78L=4 mm
Wi=0.524 mm
Subst="MSub1"
-20.3 mA
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
0 A
20.3 mA
0 A
-20.3 mA
MCROSO
Cros1
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
20.3 mA
-30.0 nA
-20.3 mA
MT EE_ADS
Tee31
W3=0.524 mm
W2=0.524 mm
W1=0.524 mmSubst="MSub1"
-20.3 mA
MLINTL291
L=2 mm
W=0.524 mm
Subst="MSub1"
-20.3 mA
MLIN
TL290
L=2 mmW=0.524 mm
Subst="MSub1"
20.3 mA
-30.0 nA
-20.3 mA
MT EE_ADS
Tee29
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
20.3 mA
-30.0 nA
-20.3 mA
MT EE_ADS
Tee30
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
-20.3 mA
MLIN
TL292
L=2 mm
W=0.524 mm
Subst="MSub1"
20.3 mA
-30.0 nA
-20.3 mA
MT EE_ADS
Tee32
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
20.3 mA
MLINTL288
L=2 mm
W=0.524 mm
Subst="MSub1"
63.3 aA
Z0805
Z0805_1
ModelType=MW
30.0 nA
sc_kmt_X7R_08055_M_19960828C27
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART _NUM=C0805C104M5R 100nF
30.0 nA
sc_kmt_C0G_06035_J_19960828
C25
SMT _Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
30.0 nA
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="Pad1"
T emperature=25
PART _NUM=C0603C101J5G 100pF
-20.3 mA
MLIN
TL289
L=2 mm
W=0.524 mm
Subst="MSub1"
-21.3 nA
20.3 mA
-20.3 mAMTEE_ADS
Tee33
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
21.3 nAMLIN
TL296
L=1 mmW=0.524 mm
Subst="MSub1"
-20.3 mAMLIN
TL295
L=1 mm
W=0.524 mm
Subst="MSub1"
189 fA
MRSTUB
Stub3
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
189 fA
MRST UB
Stub2
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
Figure 4- 34 Annotation of DC simulation of stabilized FET (Electrical model) fixed bias
(IDS=20 mA and VDS=2V, VGS=-0.17V) circuit without matching network.
Figure 4- 35 shows the schematic of stabilized LNA with S-parameter model.
From the stability factor (Figure 4- 36) it is clear that the transistor is unconditionally
stable within the bandwidth. But this condition is achieved with the expense of gain
and noise (Figure 4- 37(a) and (b)). Once the transistor is stabilized, the next step is
to design proper matching network for the LNA.
58
S2PSNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
Ref
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=4 GHz
S-PARAMETERS
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="Pad1"
PART _NUM=RC-I-0603-43R0-G 43 Ohm
Z0603
Z0603_2
ModelType=MW
Z0603
Z0603_4
ModelType=MW
Z0603
Z0603_5
ModelType=MW
Z0603
Z0603_8
ModelT ype=MW
Z0603
Z0603_6
ModelT ype=MW
Z0603
Z0603_7ModelT ype=MW
Z25_Mline
Z25_Mline_1
ModelType=MW
Z0603
Z0603_12
ModelType=MW
Z25_Ml ine
Z25_Ml ine_3
ModelType=MW
Z25_Ml ine
Z25_Ml ine_2
ModelT ype=MW
Z0603
Z0603_1
ModelType=MW
VAR
VAR4
VGS=-0.17
VDS=3
EqnVar
sc_kmt_C0G_06035_D_19960828
C36
SMT _Pad="Pad1"
T emperature=25
PART_NUM=C0603C100D5G 10pF
T erm
T erm2
Z=Z0
Num=2
Term
Term1
Z=Z0
Num=1
sc_kmt_C0G_06035_D_19960828
C37
SMT_Pad="Pad1"
Temperature=25
PART _NUM=C0603C100D5G 10pF
sr_ims_RC-I_0603_G_19950814
R3
SMT_Pad="Pad1"
PART _NUM=RC-I-0603-10R0-G 10 Ohm
Z0402
Z0402_1
ModelType=MW
zzzzzzzz
zzzzzzzz_1
ModelT ype=MW
Z0603
Z0603_11
ModelT ype=MW
Z0805
Z0805_2
ModelT ype=MW
sc_kmt_C0G_06035_D_19960828C24
SMT_Pad="Pad1"
Temperature=25
PART _NUM=C0603C100D5G 10pF
Z0603
Z0603_10
ModelType=MW
sr_ims_RC-I_0603_G_19950814
R1
SMT_Pad="Pad1"
PART _NUM=RC-I-0603-3R90-G 3.9 Ohm
SMT_Pad
Pad2
PO=-0.23 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.457 mm
W=1.22 mm
SMT_Pad
SMT_Pad
Pad1
PO=-0.15 mmSM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
V_DC
SRC1
Vdc=VDS V
I_Probe
IDS
V_DC
SRC2
Vdc=VGS V
MeasEqn
meas1EqnMeasVAR
VAR1
Z0=50
EqnVar
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
sc_kmt_C0G_06035_D_19960828
C28
SMT_Pad="Pad1"
Temperature=25
PART _NUM=C0603C100D5G 10pF
sc_kmt_X7R_08055_M_19960828
C31
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART _NUM=C0805C104M5R 100nF
sc_kmt_C0G_06035_J_19960828
C30
SMT _Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C29
SMT_Pad="Pad1"
Temperature=25
PART _NUM=C0603C101J5G 100pF
MCROSO
Cros2
W4=0.524 mm
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
T ee34
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACT IVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
MLIN
TL304
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MT EE_ADS
Tee38
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MLIN
TL303
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL302
L=2 mm
W=0.524 mmSubst="MSub1"
MT EE_ADS
Tee37
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MT EE_ADS
Tee36
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLINTL301
L=2 mm
W=0.524 mm
Subst="MSub1"
MT EE_ADS
Tee35
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL300
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL299
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
T L298
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL297
L=1 mm
W=0.524 mm
Subst="MSub1"
MRST UB
Stub5
Angle=78L=4 mm
Wi=0.524 mm
Subst="MSub1"
MRST UB
Stub4
Angle=78L=4 mm
Wi=0.524 mm
Subst="MSub1"
MLIN
T L294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MCROSO
Cros1
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
T ee31
W3=0.524 mm
W2=0.524 mm
W1=0.524 mmSubst="MSub1"
MLIN
T L291
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
T L290
L=2 mmW=0.524 mm
Subst="MSub1"
MTEE_ADS
T ee29
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
T ee30
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
T L292
L=2 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
T ee32
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLINT L288
L=2 mm
W=0.524 mm
Subst="MSub1"
Z0805
Z0805_1
ModelType=MW
sc_kmt_X7R_08055_M_19960828C27
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART _NUM=C0805C104M5R 100nF
sc_kmt_C0G_06035_J_19960828
C25
SMT _Pad="Pad1"
T emperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="Pad1"
Temperature=25
PART _NUM=C0603C101J5G 100pF
MLIN
T L289
L=2 mm
W=0.524 mm
Subst="MSub1"
MT EE_ADS
Tee33
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL296
L=1 mm
W=0.524 mm
Subst="MSub1"
MLIN
T L295
L=1 mm
W=0.524 mm
Subst="MSub1"
MRSTUB
Stub3
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
MRSTUB
Stub2
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
Figure 4- 35 Schematic of stabilized FET(S-parameter model) without matching network.
5 6 7 8 94 10
0.5
1.0
1.5
0.0
2.0
Frequency GHz
Sta
bili
ty F
acto
r K
Figure 4- 36 Stability factor vs frequency characteristic after stabilization with S-parameter
model.
5 6 7 8 94 10
8
10
12
14
16
6
18
Frequency GHz
Pow
er
Gain
dB
(S(2
,1))
5 6 7 8 94 10
0.6
0.8
1.0
1.2
1.4
0.4
1.6
Frequency GHz
Nois
e F
igu
re d
B
(a) (b)
Figure 4- 37 Power gain and noise figure after stabilization with S-parameter model.
Actual noise figure
Minimum noise figure
59
4.12.1 Matching Network Design at 8.5 GHz
Matching network design is the critical task of an LNA. At first the matching
network is designed with lumped elements then ideal transmission line and microstrip
line are used. Matching network is designed step by step using the amplifier design
guide and Smith chart tool in ADS.
All microstrip lines are transferred into layout components of Figure 4- 35.
Figure 4- 38 shows the modified schematic of LNA with layout component. The
microstrip line before DC blocking or coupling capacitor is ignored for the
simplicity. This modification will help to make the matching network easily. But
once the proper matching network is completed, then removed microstrip line is put
in front of coupling capacitor. And finally the matching network is optimized.
sr_i ms_RC-I_0603_G_19950814
R1
SMT_Pad="Pad3"
PART_NUM=RC-I-0603-3R90-G 3.9 Ohm
sr_ims_RC-I_0603_G_19950814
R3
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
sc_kmt_X7R_08055_M_19960828
C32
SMT_Pad="Pad2"
Temperature=25
Vtes t=1
PART_NUM=C0805C104M5R 100nF
sc_kmt_C0G_06035_J_19960828
C33
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C34
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_D_19960828
C35
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_D_19960828
C31
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_J_19960828
C28
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C29
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_08055_M_19960828
C30
SMT_Pad="Pad2"
Temperature=25
Vtes t=1
PART_NUM=C0805C104M5R 100nF
Z24m
Z24m_1
ModelType=MW
St
ub
3
St
ub
2
MR
ST
UB
MR
ST
UB
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
SMT_Pad
Pad3
PO=-0.125 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.25 mm
W=0.5 mm
SMT_Pad
SMT_Pad
Pad2
PO=-0.228 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.457 mm
W=1.22 mm
SMT_Pad
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad Opti ons
Opti ons1
Tnom=25
Temp=16.85
OPTIONS
MeasEqn
meas1E qnMeas
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Zin
Zin1
Zin1=zi n(S11,PortZ1)
Zin
N
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=4 GHz
S-PARAMETERS
VAR
VAR1
Z0=50
EqnVar
sc_kmt_C0G_06035_D_19960828
C36
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
Term
Term1
Z=Z0
Num=1 Z0603
Z0603_1
ModelType=MW
VAR
VAR4
VGS=-0.17
E qnV ar
Z24m
Z24m_2
ModelType=MW
St
ub
3
St
ub
2
MR
ST
UB
MR
ST
UB
V_DC
SRC2
Vdc=VGS V
I_Probe
IDS
V_DC
SRC1
Vdc=VDS V
VAR
VAR3
VDS=3
E qnV ar
Z0402
Z0402_1
ModelType=MW
Z0603
Z0603_2
Model Type=MW
Z25_Ml ine
Z25_Ml ine_1
ModelType=MW
Term
Term2
Z=Z0
Num=2
sc_kmt_C0G_06035_D_19960828
C37
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
zzzzzzzz
zzzzzzzz_1
ModelType=MW
S2P
SNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
Ref
Figure 4- 38 Layout component.
In order to minimize the noise with available gain, noise figure approach has
been used for the matching network. Figure 4- 39 shows the input and output
termination conditions of Figure 4- 38 at the higher band i.e. 8.5 GHz. It is good to
have matching at the higher band that gives less noise over the entire band [14].
0.639 / -101.550
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
17.8 - j37.6 13.57365.7 + j532.m
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.651
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
Figure 4- 39 Matching for noise figure at 8.5 GHz.
60
4.12.1.1 Matching Network by Lumped Elements
Noise figure does not depend on the output matching network. So referring to
Figure 4- 39, it is necessary to make such an input matching network that will be
complex conjugate of 17.3-j37.6. Once the input matching network is designed, a
output matching network has to design to get flat gain over the bandwidth.
We have 50 ohm termination. So In the smith chart tool, we have chosen
source as a 50 ohm and the load is the complex conjugate of Zopt i.e. ZL=*Zopt =
17.8+j37.6. Using Smith chart tool (Figure 4- 40) we have design multi section input
matching network (Figure 4- 41) by ideal lumped elements. Multi section or Π-
network gives larger bandwidth compare to L-section matching network [15].
Figure 4- 40 Smith chart of input matching network by lumped elements.
Figure 4- 41 Input matching network where L1=1.54 nH, L2=1.87 nH, L3=1.02 nH, L4=1.11
nH,C1=1.2 pF, C2=1.5 pF, C3=1.55 and C4=0.42 pF pF.
0.010 / 135.898
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
49.3 + j712.m 13.57365.7 + j532.m
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.651
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
Figure 4- 42 Matching condition at 8.5 GHz after putting input matching network.
From the simulation result (Figure 4- 42) it is clear the input is matched with
50 ohm termination at 8.5 GHz. The simulated noise figure is shown in Figure 4- 43,
where noise figure (star line) is same as minimum noise (solid line). As seen in
Figure 4- 42 , the output is close to the 50 ohm so we have ignored the output
matching network for this type of matching network only.
L1 L2 L3
C1 C3 C3
Zload=*Zopt
C4
L4
61
5 6 7 8 94 10
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.4
2.0
Frequency GHz
Nois
e F
igure
dB
Figure 4- 43 Comparison between Noise figure (star line) and minimum noise (solid line).
4.12.1.2 Microstrip Matching Network
Using the same procedure as given in previous section, we have designed multi
section input matching network with microstrip line. We have transferred the
microstrip line to layout component. Then we optimize the layout component of input
network. Figure 4- 44 shows the optimized input matching network. We have used
Roger, RO4350B substrate that is already defined in section 4.1. With the help of
Line Calc. tool, we have found the width and length.
Figure 4- 44 Input matching network with microstrip, L1=2.1 mm, L2=2 mm, L3=2 mm, L4=3.5
mm, L5=3.57 mm, L6=1.25 mm, L7=2.38 mm and W=0.524 mm.
6 7 8 95 10
8
10
12
14
16
6
18
Frequency GHz
Pow
er G
ain
dB
(S(2
,1))
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.4
2.0
Frequency GHz
Nois
e F
igure
dB
(a) (b)
Figure 4- 45 Power gain and noise figure (star line) vs frequency with input matching network.
0.020 / -17.602
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
52.0 - j638.m 13.33238.7 + j35.1
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.852
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
Figure 4- 46 Matching condition at 8.5 GHz after putting input microstrip matching network.
ZS=50 Ω ZLoad=*Zopt
Actual noise figure
Minimum noise figure
62
From Figure 4- 45 (b) it is clear that compare to lumped elements matching
network, microstrip matching network gives smaller noise figure over the bandwidth.
We can see from Figure 4- 46 that output is far from matching. So we have to make
output matching network for flat power gain over the bandwidth.
In the same way using the ADS design tool we have designed the output
matching network (Figure 4- 47). Figure 4- 48 shows the LNA with input and output
matching network. After adding the output matching network, the power gain (a)) has
increased and becomes more flat than the power gain without output matching
network.
Figure 4- 47 Output matching network with microstrip line, L1=2 mm, L2=7 mm, L3=2 mm,
L4=2.5mm, L5=3mm, L6=2 mm, L7=4mm and W=0.524mm.
6 7 8 95 10
8
10
12
14
16
6
18
Frequency GHz
Pow
er
Gain
dB
(S(2
,1))
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.4
2.0
Frequency GHz
Nois
e F
igure
dB
(a) (b)
Figure 4- 48 Power gain and noise figure (star line) vs frequency with input and output network.
4.12.2 Matching Network Design at 9 GHz
In this design we will use all microstrip components instead of individual
layout component. After getting IMN and OMN we will create complete layout
component of the LNA. In the previous matching network design 8.5 GHz was
chosen. As there was a sharp change in gain and noise after 8.5 GHz so this time we
will design matching network at 9 GHz.
We have already seen that matching network with lumped elements does not
give desired large bandwidth compare to microstrip line. So we will design matching
network with microstrip line only. This time we will slightly deviate from the
traditional way of designing matching network. Using LineCalc tools in the ADS, we
have noticed that there is a negligible difference of transmission line width at 8.5 and
9 GHz. So we will start designing matching network with 8.5 GHz in the Smith chart
utility tool then we will optimize it with 9 GHz.
ZLoad=50 Ω
ZS=*ZLoad=38.7-j35.1
Actual noise figure
Minimum noise figure
63
Figure 4- 49 shows the LNA without matching network and do not have any
layout component of capacitor and resistor footprint. For the FET, we have used
exact size of foot print with microstrip line instead of layout components.
S2P
SNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
Ref
V_DC
SRC4
Vdc=VGS V
S_ParamSP1
CalcNoise=yes
Step=0.1 GHzStop=10 GHz
Start=5 GHz
S-PARAMETERS
TermTerm1
Z=50 Ohm
Num=1
sc_kmt_C0G_06035_D_19960828C42
SMT_Pad="Pad1"PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_D_19960828
C43
SMT_Pad="Pad1"PART_NUM=C0603C100D5G 10pF
SMT_Pad
Pad3
PO=-0.125 mmSM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"L=0.25 mm
W=0.5 mm
SMT_Pad
VAR
VAR2
VGS=-0.17
VDS=3
Eqn
Var
Zin
Zin1Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_LibFile=Nominal
MeasEqnmeas1
Eqn
Meas
VARVAR1
Z0=50
EqnVar
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"SMO=0.15 mm
PadLayer="bond"L=0.3 mm
W=0.8 mm
SMT_PadOptionsOptions1
Tnom=25Temp=16.85
OPTIONS
MSUBMSub1
Rough=0.001 mm
TanD=0.0037T=0.035 mm
Hu=1.0e+033 mmCond=5.8e7
Mur=1
Er=3.66H=0.254 mm
MSub
sr_avx_CR_05_J_19960828R6
SMT_Pad="Pad3"PART_NUM=CR05-3R9J 3.9 Ohm
Term
Term2
Z=50 Ohm
Num=2
sr_ims_RC-I_0603_G_19950814R2
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
MLINTL318
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLINTL317
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLINTL320
L=0.5 mmW=0.65 mm
Subst="MSub1"
MLIN
TL319
L=0.5 mm
W=0.65 mm
Subst="MSub1"
sc_kmt_C0G_06035_D_19960828C24
SMT_Pad="Pad1"
PART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_D_19960828C41
SMT_Pad="Pad1"PART_NUM=C0603C1R0D5G 1pF
MLIN
TL306
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLIN
TL305
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLIN
TL307
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLIN
TL292
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLIN
TL291
L=1.5 mmW=0.524 mm
Subst="MSub1"
MLIN
TL290
L=1.5 mmW=0.524 mm
Subst="MSub1"
sc_kmt_X7R_06035_J_19960828C45
SMT_Pad="Pad1"PART_NUM=C0603C103J5R 10nF
sc_kmt_C0G_06035_J_19960828C39
SMT_Pad="Pad1"PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828C40
SMT_Pad="Pad1"PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="Pad1"PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C25
SMT_Pad="Pad1"
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_06035_J_19960828
C44
SMT_Pad="Pad1"
PART_NUM=C0603C103J5R 10nF
MCROSOCros1
W4=0.524 mmW3=0.524 mm
W2=0.524 mm
W1=0.524 mmSubst="MSub1"
MRSTUB
Stub3
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
MLIN
TL294
L=5.22 mm
W=0.524 mmSubst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MRSTUB
Stub4
Angle=78
L=4 mmWi=0.524 mm
Subst="MSub1"
MLINTL304
L=2 mm
W=0.524 mmSubst="MSub1"
MLINTL288
L=2 mm
W=0.524 mmSubst="MSub1"
MTEE_ADS
Tee32
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee30
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee29
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee31
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
V_DCSRC3
Vdc=VDS V
I_ProbeIDS1
sr_ims_RC-I_0603_G_19950814R4
SMT_Pad="Pad1"PART_NUM=RC-I-0603-10R0-G 10 Ohm
MTEE_ADS
Tee36
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee37
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee35
W3=0.524 mm
W2=0.524 mmW1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee38
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL308
L=2 mm
W=0.524 mmSubst="MSub1"
MLINTL289
L=2 mm
W=0.524 mmSubst="MSub1"
MCROSOCros2
W4=0.524 mmW3=0.524 mm
W2=0.524 mm
W1=0.524 mmSubst="MSub1"
MTEE_ADS
Tee34
W3=0.524 mmW2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MRSTUBStub6
Angle=78
L=4 mm
Wi=0.524 mmSubst="MSub1"
MLIN
TL299
L=5.22 mmW=0.524 mm
Subst="MSub1"
MRSTUBStub5
Angle=78
L=4 mm
Wi=0.524 mmSubst="MSub1"
Figure 4- 49 LNA before matching network.
64
4.12.2.1 Input Matching Network design
Figure 4- 50 shows the template of LNA design simulation result at 8.5 GHz
before matching network. Same procedure is used to design matching network as
before done in the previous section 4.42.1. Here only dsign steps are given in
graphically instead of details description.
0.560 / -128.393
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
17.1 - j21.8 12.81027.2 - j30.4
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.581
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
m5freq=dB(S21)=15.812
6.000GHz
m6freq=dB(S21)=9.893
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
10
12
14
16
18
8
20
freq, GHz
Pgain
_assoc
MA
GdB
(S21) m5
m6
m5freq=dB(S21)=15.812
6.000GHz
m6freq=dB(S21)=9.893
9.000GHz
m7freq=nf(2)=1.119
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10
.0
0.6
0.8
1.0
1.2
0.4
1.4
freq, GHz
NF
min
nf(
2)
m7
m7freq=nf(2)=1.119
9.000GHz
Maximum Available Gain, Associated Power Gain (input matched for NFmin, output then conjugately matched), and dB(S21)
Minimum Noise Figure, dB,and Noise Figure with Z0Ohm terminations
(a) (b)
(c)
Figure 4- 50 Simulation result of LNA at 8.5 GHz matching point without matching network.
Figure 4- 51 Smith chart for IMN design at 8.5 GHz.
65
Zsource= 50 Ohm Zload= *Zopt=17.1+j21.8
Port
P1
MLOC
TL351
L=3.75 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee62
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL352
L=3 mm
W=0.524 mm
Subst="MSub1"
Port
P2
MTEE_ADS
Tee61
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee60
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLOC
TL355
L=1.37 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL354
L=1.55 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL353
L=0.94 mm
W=0.524 mm
Subst="MSub1"
Figure 4- 52 IMN at 8.5 GHz before optimize.
As we need to put signal with SMA contact so we need some margin at the
input side of the matching network. That is why a small length (two mm) microstrip
line is added and IMN is optimized with this line at 9 GHz.
Port
P2
MLIN
TL362
L=2 mm
W=0.524 mm
Subst="MSub1"
Port
P1
MTEE_ADS
Tee65
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee64
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee63
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL361
L=3.3 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL360
L=3.375 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL359
L=1.395 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL358
L=1.35 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL357
L=1.07 mm
W=0.524 mm
Subst="MSub1"
Figure 4- 53 IMN at 9 GHz after optimize.
7.411E-5 / 100.043
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
50.0 + j7.30m 12.02528.5 - j32.5
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.805
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
m5freq=dB(S21)=15.796
6.000GHz
m6freq=dB(S21)=10.995
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
8
10
12
14
16
18
6
20
freq, GHz
Pgain
_assoc
MA
GdB
(S21)
m5
m6
m5freq=dB(S21)=15.796
6.000GHz
m6freq=dB(S21)=10.995
9.000GHz
m7freq=nf(2)=0.805
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10
.0
0.8
1.0
1.2
1.4
1.6
0.6
1.8
freq, GHz
NF
min
nf(
2)
m7
m7freq=nf(2)=0.805
9.000GHz
Maximum Available Gain, Associated Power Gain (input matched for NFmin, output then conjugately matched), and dB(S21)
Minimum Noise Figure, dB,and Noise Figure with Z0Ohm terminations
(a) (b)
(c)
Figure 4- 54 Simulation result of LNA with IMN after optimization.
66
4.12.2.2 Output Matching Network Design
Figure 4- 55 shows the Smith chart tool of ADS for designing the matching
network at 9 Ghz. Same procedure is used to design matching network as before done
in the previous section. In the same way only dsign steps are given in graphically
instead of description.
Figure 4- 55 Smith chart for OMN design at 9 GHz.
Zsource= 50 OhmZload= *Zload=28.5+32.5
Port
P1
MLOC
TL366
L=2.67 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee68
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
Port
P2
MTEE_ADS
Tee67
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee66
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL365
L=4.36 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL364
L=1.66 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL363
L=3.42 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL362
L=1.66 mm
W=0.524 mm
Subst="MSub1"
Figure 4- 56 OMN at 9 GHz before optimize.
67
0.002 / 63.927
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
50.1 + j175.m 11.86151.5 + j19.6
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.813
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
m5freq=dB(S21)=15.601
6.000GHz
m6freq=dB(S21)=11.697
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
8
10
12
14
16
18
6
20
freq, GHz
Pgain
_assoc
MA
GdB
(S21)
m5
m6
m5freq=dB(S21)=15.601
6.000GHz
m6freq=dB(S21)=11.697
9.000GHz
m7freq=nf(2)=0.813
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10
.0
0.8
1.0
1.2
1.4
1.6
0.6
1.8
freq, GHz
NF
min
nf(
2)
m7
m7freq=nf(2)=0.813
9.000GHz
Maximum Available Gain, Associated Power Gain (input matched for NFmin, output then conjugately matched), and dB(S21)
Minimum Noise Figure, dB,and Noise Figure with Z0Ohm terminations
(a) (b)
(c)
Figure 4- 57 Simulation result of LNA with optimized IMN and unutilized OMN.
We need extra margin at the out put of the matching network in order to
receive the signal. So we have added a small length (2 mm) of microstrip line then
we have optimized the matching network
Port
P2
Port
P1
MTEE_ADS
Tee71
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee70
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee69
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1" MLIN
TL373
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL372
L=3.91 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL371
L=1.67 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL370
L=2.41 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL369
L=1.32 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL368
L=2.7 mm
W=0.524 mm
Subst="MSub1"
Figure 4- 58 OMN at 9 GHz after optimization.
Figure 4- 59 shows the complete schematic of the LNA with input and out put
matching network.
68
MTE E_ADS
Tee63
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTE E_ADS
Tee64
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE _ADS
Tee65
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL359
L=3.91 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL360
L=1.67 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL358
L=2.41 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL357
L=1.32 mm
W=0.524 mm
Subst="MS ub1"
MLIN
TL361
L=2.7 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL367
L=2 mm
W=0.524 mm
Subst="MSub1"
Term
Term1
Z=50 Ohm
Num=1
Term
Term2
Z=50 Ohm
Num=2
MLOC
TL339
L=1.07 mm
W=0.524 mm
S ubst="MSub1"
MLOC
TL350
L=1.35 mm
W=0.524 mm
S ubst="MSub1"
MLIN
TL346
L=1.395 mm
W=0.524 mm
Subst="MSub1"
MLOC
TL344
L=3.375 mm
W=0.524 mm
S ubst="MSub1"
MLIN
TL340
L=3.3 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL356
L=2 mm
W=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee59
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee56
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MS ub1"
MTEE_ADS
Tee55
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MRSTUB
Stub5
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
MLIN
TL299
L=5.22 mm
W=0.524 mm
Subst="MS ub1"
MRS TUB
Stub6
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
MTE E_ADS
Tee34
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MCROSO
Cros2
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MS ub1"
MLIN
TL289
L=2 mm
W=0.524 mm
Subst="MS ub1"
MLIN
TL308
L=2 mm
W=0.524 mm
Subst="MS ub1"
MTEE_ADS
Tee38
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
S ubst="MSub1"
MTEE_ADS
Tee35
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
S ubst="MSub1"
MTEE_ADS
Tee37
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee36
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
V_DC
SRC4
Vdc=VGS V
I_Probe
IDS1
V_DC
SRC3
Vdc=VDS V
MTEE_A DS
Tee31
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_A DS
Tee29
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_A DS
Tee30
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MTEE_A DS
Tee32
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL288
L=2 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL304
L=2 mm
W=0.524 mm
Subst="MSub1"
MRSTUB
Stub4
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
MTEE_ADS
Tee33
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
Subst="MSub1"
MLIN
TL294
L=5.22 mm
W=0.524 mm
Subst="MSub1"
MRSTUB
Stub3
Angle=78
L=4 mm
Wi=0.524 mm
Subst="MSub1"
MCROSO
Cros1
W4=0.524 mm
W3=0.524 mm
W2=0.524 mm
W1=0.524 mm
S ubst="MSub1"
sc_kmt_X7R_06035_J_19960828
C44
SMT_Pad="Pad1"
PART_NUM=C0603C103J5R 10nF
sc_kmt_C0G_06035_J_19960828
C25
SMT_Pad="Pad1"
PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="P ad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C40
SMT_Pad="Pad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C39
S MT_Pad="Pad1"
P ART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_06035_J_19960828
C45
S MT_Pad="Pad1"
P ART_NUM=C0603C103J5R 10nF
MLIN
TL290
L=1.5 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL291
L=1.5 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL292
L=1.5 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL307
L=1.5 mm
W=0.524 mm
Subst="MS ub1"
MLIN
TL305
L=1.5 mm
W=0.524 mm
Subst="MS ub1"
MLIN
TL306
L=1.5 mm
W=0.524 mm
Subst="MS ub1"
sc_kmt_C0G_06035_D_19960828
C41
S MT_Pad="Pad1"
P ART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_D_19960828
C24
SMT_Pad="P ad1"
PART_NUM=C0603C1R0D5G 1pF
MLIN
TL319
L=0.5 mm
W=0.65 mm
S ubst="MSub1"
MLIN
TL320
L=0.5 mm
W=0.65 mm
S ubst="MSub1"
MLIN
TL317
L=1.5 mm
W=0.524 mm
Subst="MSub1"
MLIN
TL318
L=1.5 mm
W=0.524 mm
Subst="MSub1"
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="P ad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
sr_avx_CR_05_J_19960828
R6
SMT_Pad="Pad3"
PART_NUM=CR05-3R9J 3.9 Ohm
S2P
SNP1
File="NE3512S 02v2_2-18_2_20.s2p"
21
R e f
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
S MT_Pad
P ad1
P O=-0.15 mm
S M_Layer="solder_mask"
S MO=0.15 mm
P adLayer="bond"
L=0.3 mm
W=0.8 mm
S MT_Pad
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=5 GHz
S-PARAMETERS
VAR
VAR1
Z0=50
EqnVar
MeasEqn
meas1Eqn
M eas
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIB RARY_Lib
Fi le=Nominal
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
VA R
VA R2
VGS=-0.17
VDS=3
EqnVar
SMT_Pad
Pad3
PO=-0.125 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.25 mm
W=0.5 mm
SMT_Pad
sc_kmt_C0G_06035_D_19960828
C43
SMT_Pad="P ad1"
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_D_19960828
C42
SMT_Pad="Pad1"
PART_NUM=C0603C100D5G 10pF
Figure 4- 59 LNA with optimize IMN and OMN at 9 GHz.
Figure 4- 60 shows the template of complete schematic level simulation of the
LNA at 9 GHz matching network. Figure 4- 60 contains power gain (a), noise figure
(b) matching (c) information.
0.002 / 60.518
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
50.1 + j157.m 11.86750.0 + j808.m
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.813
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
m7freq=nf(2)=0.813
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10
.0
0.8
1.0
1.2
1.4
1.6
0.6
1.8
freq, GHz
NF
min
nf(
2)
m7
m7freq=nf(2)=0.813
9.000GHz
Maximum Available Gain, Associated Power Gain (input matched for NFmin, output then conjugately matched), and dB(S21)
Minimum Noise Figure, dB,and Noise Figure with Z0Ohm terminations
(a) (b)
(c)
m5freq=dB(S21)=15.696
6.000GHz
m6freq=dB(S21)=11.863
9.000GHz
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
8
10
12
14
16
18
6
20
freq, GHz
Pgain
_assoc
MA
GdB
(S21)
m5
m6
m5freq=dB(S21)=15.696
6.000GHz
m6freq=dB(S21)=11.863
9.000GHz
Figure 4- 60 Simulation result of LNA with IMN and OMN.
69
Figure 4- 60 shows the complete schematic look like simulation of LNA with
IMN and OMN. Figure 4- 61 shows the complete layout of LNA with IMN and
OMN.
J11
J11_1
ModelType=MW
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
V_DC
SRC3
Vdc=VDS V
I_Probe
IDS1
Term
Term2
Z=50 OhmNum=2
V_DCSRC4
Vdc=VGS V
sc_kmt_X7R_06035_J_19960828
C45
SMT_Pad="Pad1"
PART_NUM=C0603C103J5R 10nF
sc_kmt_C0G_06035_J_19960828
C39
SMT_Pad="Pad1"PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C40
SMT_Pad="Pad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_D_19960828C41
SMT_Pad="Pad1"
PART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_D_19960828
C24
SMT_Pad="Pad1"PART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_J_19960828C13
SMT_Pad="Pad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C25
SMT_Pad="Pad1"
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_06035_J_19960828
C44
SMT_Pad="Pad1"
PART_NUM=C0603C103J5R 10nF
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
sc_kmt_C0G_06035_D_19960828
C43
SMT_Pad="Pad1"PART_NUM=C0603C100D5G 10pF
sr_avx_CR_05_J_19960828
R6
SMT_Pad="Pad3"
PART_NUM=CR05-3R9J 3.9 Ohm
S2P
SNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
Ref
S_Param
SP1
CalcNoise=yesStep=0.1 GHz
Stop=10 GHz
Start=2 GHz
S-PARAMETERS
sc_kmt_C0G_06035_D_19960828
C42
SMT_Pad="Pad1"PART_NUM=C0603C100D5G 10pF
SMT_PadPad3
PO=-0.125 mm
SM_Layer="solder_mask"SMO=0.15 mm
PadLayer="bond"
L=0.25 mm
W=0.5 mm
SMT_Pad
VAR
VAR2
VGS=-0.17
VDS=3
EqnVar
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
MeasEqnmeas1
EqnM eas
VAR
VAR1
Z0=50
EqnVar
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"SMO=0.15 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_PadOptions
Options1
Tnom=25
Temp=16.85
OPTIONS
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mmHu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66H=0.254 mm
MSub
TermTerm1
Z=50 Ohm
Num=1
Figure 4- 61 complete layout look like LNA with IMN and OMN.
Figure 4- 62 shows the template of complete layout simulation of the LNA at 9 GHz
matching network. Figure 4- 62 contains power gain (a), noise figure (b) matching (c)
information.
0.206 / 121.172
Source ReflectionCoefficient for Minimum NF
Zopt for NFmin
38.1 + j14.0 11.83341.4 - j33.9m
Power Gain with theseSource and Load Reflection Coefficients
Conjugate Match Load Impedance if Source Reflection Coefficient is Sopt for Minimum NF
Matching For Noise Figure
NFmin, dB
0.947
Zopt
Conjugate match Zload if source impedance is Zopt
DUT* *DUT= Device Under Test(simulated circuit or device)
m7freq=nf(2)=1.013
9.000GHz
m10freq=nf(2)=0.895
6.000GHz
3 4 5 6 7 8 92 10
5
10
15
20
0
25
freq, GHz
NF
min
nf(
2)
m7m10
m7freq=nf(2)=1.013
9.000GHz
m10freq=nf(2)=0.895
6.000GHz
Maximum Available Gain, Associated Power Gain (input matched for NFmin, output then conjugately matched), and dB(S21)
Minimum Noise Figure, dB,and Noise Figure with Z0Ohm terminations
(a)(b)
(c)
m8freq=dB(S21)=14.913
6.000GHz
m9freq=dB(S21)=11.382
9.000GHz
3 4 5 6 7 8 92 10
-20
-10
0
10
-30
20
freq, GHz
Pgain
_assoc
dB
(S21)
m8
m9m8freq=dB(S21)=14.913
6.000GHz
m9freq=dB(S21)=11.382
9.000GHz
Figure 4- 62 Forward transmission (solid line) and transducer gain (dot line).
70
4.12.3 Layout of RF choke
Figure 4- 63 shows the complete layout of the RF choke which is the first
section of LNA after stabilization.
Figure 4- 63 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF, C4=100nF
and R1=43 Ω.
4.13 References
[1] Adriana Serban, Ultra-Wideband Low-Noise Amplifier and Six-Port
Transceiver for High Speed Data Transmission. Linköping Studies in
Science and Technology, Dissertation No. 1295.
[2] Roger R04350B data sheet, www.rogerscorp.com [3] NEC Electronics, www.necel.com
[4] Transistor model,www.wikipedia.org
[5] Guillermo Gonzalaz, Microwave Transistor Amplifiers Analysis and Design.
Prentice Hall, USA 1997.
[6] Robert L. Boylestad, Louis Nashelsky, Electronic Devices and Circuit
Theory. Prentice Hall, India, 2000.
[7] Microwave FET Tutorial, www.microwaves101.com/index.cfm.
[8] RFIC Tutorial,
www.odyseus.nildram.co.uk/RFMicrowave_Theory_Files/Bias_Circuits.pdf
[9] M. Goldfarb and R. Pucel. "Modeling Via Hole Grounds in Microstrip," IEEE
Microwave and Guided Wave Letters , Vol. 1, No. 6, June 1991, pp. 135-137
[10] Richard Fiore, Selecting RF chip Capacitor for Wireless Application.
Technical note, American Technical Ceramics.
71
[11] Richard Fiore, Capacitors in Broadband applications. Technical note,
American Technical Ceramics.
[12] Technical manual, Vendor Component libraries- September 2004. Agilent
Technologies
[13] Adriana Serban, Magnus Karlsson and Shaofang Gong, “Study of Bias
Networks with RF Choke for Ultra-Wideband Systems”. IEEE Microwave
and Wireless Components Letters.
[14] Adriana Serban and Shaofang Gong, “Ultra-Wideband Low-Noise Amplifier
Design for 3.1-4.8 GHz”.
[15] Reinhold Ludwig and Pavel Bretchko, RF Circuit Design Theory and
Application. Prentice-Hall, USA, 2000.
72
5 LNA Implementation: Simulation Results and
Measurements
This chapter is divided into three sections; simulation result, measurement
and post-manufactured simulation. Simulation is done using ADS design tool from
Agilent Technologies and measurements is done using Agilent 8703A vector network
analyzer
5.1 Simulation Results
All necessary simulation results are given in this section.
5.1.1 Via Model Simulation
(h) ADS via model(0.4 mm)
(g) One 0.2 mm via
(f) One 0.4 mm via with 1.6 mm microstrip line
(e) Two 0.4 mm via with 5 mm microstrip line
(d) One 0.4 mm via with 5 mm microstrip line
(c) Six 0.4 mm via
(b) Three 0.4 mm via
(a) One 0.4 mm via
VIA2
V2
T=0.00375 mm
H=0.254 mm
D=0.4 mm
Term
Term16
Z=50 Ohm
Num=16
Term
Term15
Z=50 Ohm
Num=15
Z11
Z11_2
ModelType=MW
Term
Term10
Z=50 Ohm
Num=10
Term
Term12
Z=50 Ohm
Num=12
Term
Term14
Z=50 Ohm
Num=14
Term
Term13
Z=50 Ohm
Num=13
Z14
Z14_2
ModelType=MW
Z16
Z16_2
ModelType=MW
Term
Term9
Z=50 Ohm
Num=9
Term
Term11
Z=50 Ohm
Num=11
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
S_Param
SP1
Step=0.1 GHz
Stop=18 GHz
Start=0 GHz
S-PARAMETERS
DisplayTemplate
disptemp1
"S_Params_Quad_dB_Smith"
TempDisp
Z15
Z15_2
ModelType=MW
Term
Term7
Z=50 Ohm
Num=7
Term
Term8
Z=50 Ohm
Num=8
Term
Term6
Z=50 Ohm
Num=6
Term
Term1
Z=50 Ohm
Num=1
Term
Term3
Z=50 Ohm
Num=3
Term
Term4
Z=50 Ohm
Num=4
Term
Term2
Z=50 Ohm
Num=2
Z08
Z08_2
ModelType=MW
K17
K17_2
ModelType=MW
Z12
Z12_1
ModelType=MW
Term
Term5
Z=50 Ohm
Num=5
Figure 5- 1 Schematic for VIA model simulation.
73
m2freq=S(3,3)=0.981 / 171.026impedance = Z0 * (0.010 + j0.078)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(3
,3)
m2
m2freq=S(3,3)=0.981 / 171.026impedance = Z0 * (0.010 + j0.078)
9.000GHz
m3freq=S(5,5)=0.987 / 173.531impedance = Z0 * (0.006 + j0.057)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(5
,5)
m3
m3freq=S(5,5)=0.987 / 173.531impedance = Z0 * (0.006 + j0.057)
9.000GHzm4freq=S(7,7)=0.007 / 117.233impedance = Z0 * (0.993 + j0.013)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(7
,7) m4
m4freq=S(7,7)=0.007 / 117.233impedance = Z0 * (0.993 + j0.013)
9.000GHz
m5freq=S(9,9)=0.029 / -102.230impedance = Z0 * (0.986 - j0.057)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(9
,9)
m5
m5freq=S(9,9)=0.029 / -102.230impedance = Z0 * (0.986 - j0.057)
9.000GHz
m6freq=S(11,11)=0.708 / 135.755impedance = Z0 * (0.198 + j0.393)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(1
1,1
1)
m6
m6freq=S(11,11)=0.708 / 135.755impedance = Z0 * (0.198 + j0.393)
9.000GHz
m1freq=S(1,1)=0.971 / 167.769impedance = Z0 * (0.015 + j0.107)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(1
,1)
m1
m1freq=S(1,1)=0.971 / 167.769impedance = Z0 * (0.015 + j0.107)
9.000GHz
(a) (b)
(c) (d)
(e) (f)
m7freq=S(13,13)=0.967 / 166.887impedance = Z0 * (0.017 + j0.115)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(1
3,1
3)
m7
m7freq=S(13,13)=0.967 / 166.887impedance = Z0 * (0.017 + j0.115)
9.000GHzm8freq=S(15,15)=0.999 / 177.816impedance = Z0 * (4.865E-4 + j0.019)
9.000GHz
freq (0.0000Hz to 18.00GHz)
S(1
5,1
5) m8
m8freq=S(15,15)=0.999 / 177.816impedance = Z0 * (4.865E-4 + j0.019)
9.000GHz
(h) (g)
Figure 5- 2 Input reflection coefficient of different via models of Figure 5- 1.
Figure 5- 2 shows the reflection coefficients of different via models. From
Figure 5- 2(c) tt can be seen that multiple smaller via has small reflection coefficient
74
compare to other models. So this kind of via is more suitable especially for
grounding.
5.1.2 DC Blocking Capacitor Simulation
Simulation setup of 10 pF DC blocking capacitor is given in Figure 5- 3. We
have added the footprint in order to add more parasites in the SMT models. Although
we haven’t use all models except Kemet, simulation result of four capacitors forward
transmission are shown in Figure 5- 4.
sc_mrt_MC_GRH110C0G050_D_19960828
C46
PART_NUM=GRH110C0G100D050 10pF
sc_phl_CMC_0603_5_19920918
C45
PART_NUM=222257811523 10pF
sc_atc_100_CDR11BG_J_19960828
C44
PART_NUM=ATC100A100JCA150 10pF
sc_kmt_C0G_06035_D_19960828
C36
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pFSMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
Z0603
Z0603_4
ModelType=MW
Z0603
Z0603_2
ModelType=MW
Term
Term2
Z=50 Ohm
Num=2
Term
Term5
Z=50 Ohm
Num=5
Term
Term7
Z=50 Ohm
Num=7
Term
Term4
Z=50 Ohm
Num=4
Term
Term6
Z=50 Ohm
Num=6
Z0603
Z0603_3
ModelType=MW
Term
Term8
Z=50 Ohm
Num=8
Z0603
Z0603_1
ModelType=MW
DisplayTemplate
disptemp1
"S_Params_Quad_dB_Smith"
TempDisp
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
S_Param
SP1
Step=0.1 GHz
Stop=18 GHz
Start=0 GHz
S-PARAMETERS
Zin
Zin1
Zin2=zin(S33,PortZ1)
Zin3=zin(S55,PortZ1)
Zin4=zin(S77,PortZ1)
Zin1=zin(S11,PortZ1)
Zin
N
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.48
H=0.254 mm
MSub
Term
Term1
Z=50 Ohm
Num=1
Term
Term3
Z=50 Ohm
Num=3
Figure 5- 3 Schematic for SMT capacitor model simulation.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 170 18
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
-50
10
Frequency GHz
Fo
rwa
rd T
ran
sm
issio
n d
B
Figure 5- 4 Forward transmission vs frequency characteristics for 10 pF capacitor, Kemet-solid
line star, ATC-circle line, Philips-star line and Murata-triangle line.
Kemet
Murata
ATC
Philips
75
5.1.3 RF Choke
RF choke is one of the important parts of the LNA design. This will allow the
biasing the active device and in the same time prevents the RF signal move toward
the DC line. Figure 5- 5 shows the simulation setup for the Layout of RF choke.
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
S_Param
SP1
Step=0.1 GHz
Stop=12 GHz
Start=4 GHz
S-PARAMETERS
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
SMT_Pad
Pad2
PO=-0.23 mm
SM_Layer="solder_mask"
SMO=0.12 mm
PadLayer="bond"
L=0.457 mm
W=1.22 mm
SMT_Pad
Z24DCpath
Z24DCpath_1
ModelType=MW
Term
Term1
Z=50 Ohm
Num=1
Term
Term2
Z=50 Ohm
Num=2
Term
Term3
Z=50 Ohm
Num=3
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
sc_kmt_C0G_06035_D_19960828
C35
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_J_19960828
C34
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C33
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_08055_M_19960828
C32
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART_NUM=C0805C104M5R 100nF
Figure 5- 5 Layout of RF choke with bias circuit; C1=10pF, C2=100 pF, C3=220 pF, C4=100nF
and R1=43 Ω.
C1
C3
C2
R1
C4
76
5 6 7 8 9 10 114 12
-4
-3
-2
-1
-5
0
Frequency GHz
Fo
rwa
rd T
ran
sm
issio
n d
B(S
(2,1
))
m1m2
m1freq=dB(S(2,1))=-0.497
6.000GHzm2freq=dB(S(2,1))=-0.213
9.000GHz
Figure 5- 6 Forward transmission vs frequency simulation result of Figure 5- 5.
5 6 7 8 9 10 114 12
-50
-40
-30
-60
-20
Frequency, GHz
Fo
rwa
rd T
ran
sm
issio
n d
B(S
(3,1
))
m1
m2
m1freq=dB(S(3,1))=-34.453
6.000GHzm2freq=dB(S(3,1))=-39.019
9.000GHz
Figure 5- 7 Forward transmission vs frequency simulation result of Figure 5- 5.
77
5 6 7 8 9 10 114 12
-40
-30
-20
-10
-50
0
Frequency GHz
Inp
ut R
efle
ctio
n d
BS
(1,1
) m1
m2
m1freq=dB(S(1,1))=-10.983
6.000GHzm2freq=dB(S(1,1))=-18.933
9.000GHz
Figure 5- 8 Input reflection coefficient vs frequency simulation result of Figure 5- 5.
Figure 5- 6 to Figure 5- 8 shows the simulation result of layout of RF choke.
From these results it is clear that this RF choke gives good RF blocking towards the
DC path (Port 3) and better forward transmission between port-1 and port-2 within
the required bandwidth (6-9 GHz).
5.1.4 LNA with Matching Network at 8.5 GHz
There are two LNA modules are design with slightly modifying the matching
network at 8.5 GHz and. At the same time the DC blocking and decoupling
capacitors value were changed.
LNA module-1
Figure 5- 9 shows the LNA with exact matching network which is described
in the previous chapter in section 4.12.1(Matching Network at 8.5 GHz).
78
Term
Term2
Z=Z0
Num=2Term
Term1
Z=Z0
Num=1
VAR
VAR1
Z0=50
Eq nVa r
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
Tec hInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
sc_k mt_C0G_06035_J_19960828
C29
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J 5G 220pF
I_Probe
IDS
sr_ims _RC-I_0603_G_19950814
R3
SMT_Pad="Pad1"
PART_NUM=RC- I-0603-43R0-G 43 Ohm
V_DC
SRC1
Vdc=VDS V
VAR
VAR3
VDS=3
EqnVar
sc_kmt_X7R_08055_M_19960828
C30
SMT_Pad="Pad2"
Temperature=25
Vtest=1
PART_NUM=C0805C104M5R 100nF
sc_kmt_C0G_06035_J_19960828
C28
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
VAR
VAR4
VGS=-0.17
EqnVar
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
sc _kmt_C0G_06035_J_19960828
C34
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C101J5G 100pF
sc _kmt_C0G_06035_J _19960828
C33
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_08055_M_19960828
C32
SMT_Pad="Pad2"
Temperature=25
Vtes t=1
PART_NUM=C0805C104M5R 100nF
MeasEqn
meas1Eqn
M eas
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.3 mm
W=0.8 mm
SMT_Pad
SMT_Pad
Pad2
PO=-0.228 mm
SM_Lay er="solder_mask"
SMO=0.15 mm
PadLay er="bond"
L=0.457 mm
W=1.22 mm
SMT_Pad
SMT_Pad
Pad3
PO=-0.125 mm
SM_Layer="solder_mask"
SMO=0.15 mm
PadLayer="bond"
L=0.25 mm
W=0.5 mm
SMT_Pad
MSUB
MSub1
Rough=0.001 mm
TanD=0.0037
T=0.035 mm
Hu=1.0e+033 mm
Cond=5.8e7
Mur=1
Er=3.66
H=0.254 mm
MSub
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Star t=5 GHz
S-PARAMETERS
s r_avx_CR_05_J_19960828
R5
SMT_Pad="Pad3"
PART_NUM=CR05-3R9J 3.9 Ohm
sc_kmt_C0G_06035_D_19960828
C35
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_D_19960828
C31
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
Z0402
Z0402_1
ModelTy pe=MW
Z25_Mline
Z25_Mline_1
ModelTy pe=MW
V_DC
SRC2
Vdc=VGS V
Z30
Z30_1
ModelType=MW
L7=X7 mm
L6=X6 mm
L5=X5 mm
L4=X4 mm
L3=X3 mm
L2=X2 mm
L1=X1 mm
Tee1 Tee3 Tee4Tee2TL2TL3
TL4TL5
TL6TL7
TL8
M TEE_ADS M TEE_ADS
M TEE_ADSM TEE_ADS
M LO C
M LI NM LO C
M LI N
M LO C
M LI NM LO C
VAR
VAR7
X7=2.38
X6=1.25
X5=3.57
X4=3.5
X3=2
X2=2
X1=2.1
EqnVar
Z0603
Z0603_1
ModelType=MW
Z25_Mline
Z25_Mline_2
ModelTy pe=MW
Z35
Z35_1
ModelType=MW
L7=Z7 mm
L6=Z6 mm
L5=Z5 mm
L4=Z4 mm
L3=Z3 mm
L2=Z2 mm
L1=Z1 mm
Tee1Tee3Tee4 Tee2TL8
TL7TL6
TL5TL4
TL3TL2 M TEE_ADSM TEE_ADS
M TEE_ADS M TEE_ADSM LO C M LI N
M LO C
M LI N M LO C M LI N
M LO C
VAR
VAR8
Z7=4
Z6=2
Z5=3
Z4=2.5
Z3=2
Z2=7
Z1=2
EqnVar
Z25_Mline
Z25_Mline_3
ModelType=MW
Z0603
Z0603_2
ModelType=MW
S2P
SNP1
File="NE3512S02v2_2-18_2_20.s 2p"
21
Ref
sc _kmt_C0G_06035_D_19960828
C37
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
sc_kmt_C0G_06035_D_19960828
C36
SMT_Pad="Pad1"
Temperature=25
PART_NUM=C0603C100D5G 10pF
zzzz zzzz
zzzz zzzz_1
ModelType=MW
Z24m
Z24m_1
ModelType=MW
Z24m
Z24m_2
ModelType=MW
Z08
Z08_11
ModelType=MW
Z08
Z08_10
ModelType=MW
Z08
Z08_9
ModelType=MW
Z08
Z08_8
ModelType=MW
Z08
Z08_7
ModelType=MW
Z08
Z08_6
ModelType=MW
Z08
Z08_5
ModelType=MW
Z08
Z08_4
ModelType=MW
Z08
Z08_3
ModelType=MW
Z08
Z08_2
ModelType=MW
Figure 5- 9 Simulation setup of the LNA module-1with input and out put matching networks.
Figure 5- 10 and Figure 5- 11 shows the simulation resuls of layout look like
LNA which matching networks were at 8.5 GHz. From the power gain curve (Figure
5- 10) it can be seen that the power gain is almost flat from 6 GHz to 8.5 GHz with
12.8 dB value. After 8.5 GHz the gain goes down to 10.2 dB point which is within
the design specification. And the power gain deviation between 6 GHz and 9 GHz is
2.6 dB. On the other hand from noise figure (Figure 5- 11) it can be seen that actual
noise figure is almost flat with less than 1 dB value. Since the matching was done at
8.5 GHz, so the actual noise figure is same as minimum noise figure at that
frequency. After this matching frequency actual noise frequency goes to 1.2 dB at 9
GHz which is within the design specifications.
79
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
5
10
15
0
20
Frequency GHz
Pow
er
Gain
dB
(S(2
,1))
m11
m13
m11freq=dB(S21)=12.883
6.000GHzm13freq=dB(S21)=10.260
9.000GHz
Figure 5- 10 Power gain vs frequency of LNA module-1.
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
5.0
10.0
1
2
3
4
0
5
Frequency GHz
Nois
e F
igure
dB
m14 m15
m14freq=nf(2)=0.943
6.000GHzm15freq=nf(2)=0.875
8.500GHz
Figure 5- 11 NF vs frequency (LNA module-1); star line- actual noise and solid line-minimum
noise.
LNA module-2
Figure 5- 12 shows the LNA with changing the structure of matching network
at 8.5 GHz. Same design procedure is used as described in the previous chapter in
80
section 4.12.1 (Matching Network at 8.5 GHz). Due to simplicity all descriptions are
avoided and final layout is shown here.
D10 lay
D10 lay _1
M od elTy pe=M W
V_DC
SRC2
Vdc =VGG V
VAR
VAR4
VGG= -0.17
EqnVar
s r_im s _ RC-I_0603_G_199 50814
R3
SM T_Pa d="Pad2"
PART_NUM =RC-I-0603-10R0-G 10 Ohm
V_DC
SRC3
Vdc =VDD V
VAR
VAR3
VDD=5
EqnVar
s r_im s _RC-I_0603_G_ 19950814
R4
SM T_ Pad="Pad2"
PART _NUM =RC-I-0603-1500-G 150 Ohm
Tec hInc lu de_NEC_ACTIVEL IBRARY
NEC_ACTI VELIBRARY_Lib
Fi le=Nom inal
S_Param
SP1
Calc Nois e= y es
Step=0.1 GHz
Stop=9.5 GHz
Start=5.5 GHz
S-P ARAMETERS
Opti ons
Opti ons 1
Tno m =25
Tem p=16.85
OPTIONS
M eas Eqn
m eas 1Eqn
M eas
VAR
VAR1
Z0=50
EqnVar
SM T_Pa d
Pad2
PO=0 m m
SM _Lay er="s older_m as k "
SM O=0.1 2 m m
PadLay e r="bond"
L=0.4 m m
W=0.55 m m
SM T_Pad
SM T_Pad
Pad1
PO=0 m m
SM _Lay er="s o lder_m as k "
SM O=0.16 m m
PadLay er="bo nd"
L=0.63 m m
W=0.55 m m
SM T_Pad
M SUB
M Sub1
Rough=0.001 m m
TanD=0.0037
T=0.035 m m
Hu=1.0e+033 m m
Cond=5.8e7
M ur=1
Er=3.48
H=0.254 m m
M Sub
S2P
SNP2
Ty p e=Touc hs tone
Fi le ="NE3512S02v 2_ 2-18_2_20.s 2p"
21
R e f
s c _atc _1 00_CDR12BG_B_1 9960828
C24
SM T_Pad ="Pad1"
PART_NUM =ATC100A3R0BP150 3pF
s c _atc _100 _CDR12BG_B_19 960828
C28
SM T_Pad="Pad1"
PART_NUM = ATC100A3R0BP1 50 3pF
s c _atc _100_CDR11 BG_J _19960828
C2 6
SM T_Pad="Pad1"
PART_NUM =ATC100 A100J CA150 10p F
s c _atc _100_CDR12BG_B_199608 28
C27
SM T_Pad="Pad1 "
PART_NUM =ATC100A1R5BP150 1 .5pF
s c _atc _100_ CDR12BG_B_199 60828
C33
SM T_Pad="Pad1"
PART_NUM =ATC100A1R5BP15 0 1.5pF
Term
Term 2
Z=50 Ohm
Num =2
s r_im s _RC-I_0603_G_19950 814
R6
SM T_Pad="Pad2"
PART_NUM = RC-I-0603-3R90-G 3.9 Ohm
Term
Term 1
Z=5 0 Ohm
Num =1
s c _a tc _100_CDR11BG_J _19960828
C25
SM T_ Pad="Pad1"
PART _NUM =ATC100A1 01J CA150 100pF
s c _atc _ 100_CDR12BG_B_ 19960828
C31
SM T_Pa d="Pad1"
PART_NUM =ATC100A1R5BP150 1.5pF
s c _atc _ 100_CDR11BG_J _ 19960828
C29
SM T_Pa d="Pad1"
PART_NUM =ATC100A100J CA150 10pF
s c _atc _10 0_CDR11BG_J _19 960828
C30
SM T_Pad= "Pad1"
PART_NUM =ATC100A101J CA150 100pF
s c _ atc _100_CDR12BG_B_19960828
C32
SM T_Pad="Pad1"
PART_NUM =ATC100A1R5BP150 1.5pF
Figure 5- 12 Simulation setup of the LNA module-2 with input and output matching network at
8.5 GHz
Figure 5- 13 and Figure 5- 14 shows the simulation resuls of layout look like
LNA which matching networks were at 8.5 GHz. From the power gain curve (Figure
5- 13) it can be seen that the power gain is almost flat from 6 GHz to 7.5 GHz with
14.7 dB value. After 7.5 GHz the gain goes down to 12 dB point which is within the
design specification. And the power gain deviation between 6 GHz and 9 GHz is 2.7
81
dB. On the other hand from noise figure (Figure 5- 14) it can be seen that actual noise
figure is almost flat with less than 1.1 dB value and actual noise figure is same as
minimum noise figure at 8 GHz frequency. After this matching frequency actual
noise frequency goes to 0.9 dB at 9 GHz which is within the design specifications.
6.0 6.5 7.0 7.5 8.0 8.5 9.05.5 9.5
5
10
15
0
20
Frequency GHz
Pow
er
Ga
in d
B(S
(2,1
))
m11m13
m11freq=dB(S21)=14.712
6.000GHzm13freq=dB(S21)=13.703
8.200GHz
Figure 5- 13 Power gain vs frequency of LNA module-2
6.0 6.5 7.0 7.5 8.0 8.5 9.05.5 9.5
0.7
0.8
0.9
1.0
1.1
1.2
0.6
1.3
Frequency GHz
No
ise
Fig
ure
dB
m14
m15
m14freq=nf(2)=1.066
6.000GHzm15freq=nf(2)=0.878
9.000GHz
Figure 5- 14 NF vs frequency (LNA-modele-2); star line- actual noise and solid line-minimum
noise
Table 3 LNA module-1 and -2 comparisons
LNA freq Gain NF
Module-1 At 6 GHz 12.9 dB 0.94
82
At 9 GHz 10.3 dB 0.87
At 6 GHz 14.7 dB 1.06 Module-2
At 9 GHz 13.7 dB 0.88
From this comparison it is clear both LNA module-1 and LNA module-2 meet the
design specifications.
5.1.5 LNA with Matching Network at 9 GHz
S_ParamSP1
CalcNoise=yesStep=0.1 GHz
Stop=10 GHzStart=5 GHz
S-PARAMETERS
J11
J11_1ModelType=MW
NEC_FETQ1
partName=NE3512S02_v118
sr_ims_RC-I_0603_G_19950814
R4
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-10R0-G 10 Ohm
V_DCSRC3
Vdc=VDS V
I_Probe
IDS1
TermTerm2
Z=50 OhmNum=2
V_DCSRC4
Vdc=VGS V
sc_kmt_X7R_06035_J_19960828
C45
SMT_Pad="Pad1"
PART_NUM=C0603C103J5R 10nF
sc_kmt_C0G_06035_J_19960828C39
SMT_Pad="Pad1"PART_NUM=C0603C221J5G 220pF
sc_kmt_C0G_06035_J_19960828
C40
SMT_Pad="Pad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_D_19960828C41
SMT_Pad="Pad1"PART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_D_19960828C24
SMT_Pad="Pad1"PART_NUM=C0603C1R0D5G 1pF
sc_kmt_C0G_06035_J_19960828
C13
SMT_Pad="Pad1"
PART_NUM=C0603C101J5G 100pF
sc_kmt_C0G_06035_J_19960828
C25
SMT_Pad="Pad1"
PART_NUM=C0603C221J5G 220pF
sc_kmt_X7R_06035_J_19960828C44
SMT_Pad="Pad1"PART_NUM=C0603C103J5R 10nF
sr_ims_RC-I_0603_G_19950814
R2
SMT_Pad="Pad1"
PART_NUM=RC-I-0603-43R0-G 43 Ohm
sc_kmt_C0G_06035_D_19960828C43
SMT_Pad="Pad1"PART_NUM=C0603C100D5G 10pF
sr_avx_CR_05_J_19960828R6
SMT_Pad="Pad3"PART_NUM=CR05-3R9J 3.9 Ohm
S2PSNP1
File="NE3512S02v2_2-18_2_20.s2p"
21
Ref
DC
DC1
Step=0.1
Stop=3Start=0
SweepVar="VDS"
DC
sc_kmt_C0G_06035_D_19960828
C42
SMT_Pad="Pad1"
PART_NUM=C0603C100D5G 10pF
SMT_PadPad3
PO=-0.125 mmSM_Layer="solder_mask"
SMO=0.15 mmPadLayer="bond"
L=0.25 mmW=0.5 mm
SMT_Pad
VAR
VAR2
VGS=-0.17
VDS=3
EqnVar
Zin
Zin1Zin1=zin(S11,PortZ1)
Zin
N
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_LibFile=Nominal
MeasEqn
meas1Eqn
M eas
VAR
VAR1Z0=50
EqnVar
SMT_Pad
Pad1
PO=-0.15 mm
SM_Layer="solder_mask"SMO=0.15 mm
PadLayer="bond"L=0.3 mm
W=0.8 mm
SMT_PadOptions
Options1
Tnom=25
Temp=16.85
OPTIONS
MSUBMSub1
Rough=0.001 mmTanD=0.0037
T=0.035 mmHu=1.0e+033 mm
Cond=5.8e7Mur=1
Er=3.66H=0.254 mm
MSub
Term
Term1
Z=50 Ohm
Num=1
Figure 5- 15 Simulation setup of the LNA with input and out put matching networks.
83
Figure 5- 16 and Figure 5- 17 shows the simulation resuls of layout look like
LNA which matching networks were at 9 GHz. From the power gain curve (Figure 5-
16) it can be seen that the power gain deviation is 3.5 dB between 6 GHz and 9 GHz
frequency and the average value is 11 dB which is within the design limit. But for
this design the power deviation is more compare to other two designs (Module-1 and
Module-2) On the other hand from noise figure (Figure 5- 17) it can be seen that
actual noise figure is almost flat l dB value which also meet the design specification.
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
5
10
15
0
20
Frequency GHz
Pow
er G
ain
dB
(S(2
,1))
m11
m13
m11freq=dB(S21)=14.913
6.000GHzm13freq=dB(S21)=11.382
9.000GHz
Figure 5- 16 Power gain vs frequency.
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
1.0
1.5
2.0
2.5
0.5
3.0
Frequency GHz
No
ise
Fig
ure
dB
m14m15
m14freq=nf(2)=0.895
6.000GHzm15freq=nf(2)=1.013
9.000GHz
Figure 5- 17 Noise figure vs frequency; star line- actual noise and solid line-minimum noise.
5.1.6 Comparison of two LNA
Figure 5- 18 and Figure 5- 19 show the comparison of LNA modelue-1
which matching networks were done at 8.5 GHz and LNA with matching network at
84
9 GHz. Compare to LNA module-1, the second design gives more gain in the
sidebands and less noise in the higher band. But the power gain deviation between 6
GHz and 9 GHz is less for LNA module-1 compare to LNA with matching at 9 GHz.
It is also important to have less power gain deviation within the bandwidth. So
compare to power gain deviation, LNA with 8.5 GHz matching gives better result
than LNA with 9 GHz mathing.
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
4
6
8
10
12
14
2
16
Frequency GHz
Pow
er
Gain
dB
(S(2
,1))
Figure 5- 18 Power gain vs frequency; solid line at 8.5 GHz matching and dot line at 9 GHz
matching.
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
1
2
3
4
0
5
Frequency GHz
No
ise
Fig
ure
Figure 5- 19 Noise figure vs frequency; dot line-for 9 GHz and solid line-8.5 GHz
85
5.1.7 LNA layout
After getting the RF choke we have designed the input and output matching
network. We have created two layout modules using the 8.5 GHz matching network.
From Figure 5- 20 and Figure 5- 21, it can be seen that final layout design for the
LNA is ready for manufacture. In the same time all manufacturers’ components and
via are added in the layout.
Figure 5- 20 Complete layout of LNA module-1; C1, C2, C3, C7=10 pF; C4, C8=100 pF; C5,
C9=220 pF; C6, C10=100 nF.
86
Figure 5- 21Complete layout of LNA module-2; C1, C2,C3, C7=1.5 pF; C4, C8=3 pF; C5, C9=10
pF; C6, C10=100 pF. R1=3.9 ohm, R2=10 ohm, R3=150 ohm and Q1= NE3512S02
87
5.2 Measurements
LNA module-1
After doing measurement with using Agilent 8703A vector network analyzer,
we have saved our data as a S-parameter file. Then using ADS we have extracted the
measurement data.
Measurement setup:
Frequency 5-10 GHz
VD=3 V
VG=-0.53 V (Design value was -0.17 V)
IDS=17 mA (Design value was 20 mA)
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Term
Term2
Z=50 Ohm
Num=2
Term
Term1
Z=50 Ohm
Num=1
VAR
VAR1
Z0=50
EqnVar
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
MeasEqn
meas1Eqn
Meas
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=10 GHz
Start=4 GHz
S-PARAMETERS S2P
SNP1
File="RESULT.S2P"
21
Ref
Figure 5- 22 Schematic for data display of measured LNA modele-1.
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
4.0
10.0
5
10
15
0
20
Frequency GHz
Pow
er G
ain
dB(S
(2,1
))
m2
m1
m2freq=dB(S21)=7.314
8.500GHzm1freq=dB(S21)=14.774
6.000GHz
Figure 5- 23 Power gain of the LNA after implementation.
LNA module-2
88
S2P
SNP1
Type=Touchstone
File="A.S2P"
21
Ref
Options
Options1
Tnom=25
Temp=16.85
OPTIONS
MeasEqn
meas1Eqn
Meas
Term
Term2
Z=50 Ohm
Num=2
Term
Term1
Z=50 Ohm
Num=1
S_Param
SP1
CalcNoise=yes
Step=0.1 GHz
Stop=9.5 GHz
Start=5.5 GHz
S-PARAMETERS
VAR
VAR1
Z0=50
EqnVar
TechInclude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
File=Nominal
Zin
Zin1
Zin1=zin(S11,PortZ1)
Zin
N
Figure 5- 24 Schematic for data display of measured LNA modele-2
6.0 6.5 7.0 7.5 8.0 8.5 9.05.5 9.5
4
5
6
7
8
9
3
10
Frequency GHz
Po
we
r G
ain
dB
m5
m6
m5freq=dB(S(2,1))=9.180
6.000GHzm6freq=dB(S(2,1))=4.220
9.000GHz
Figure 5- 25 LNA module-2
From the measurement data it is clear that the implemented LNA’s gain is less than
the specifications.
89
6.0 6.5 7.0 7.5 8.0 8.5 9.05.5 9.5
0
5
10
15
-5
20
Frequency GHz
Pow
er G
ain
dB
m3
m4
m1
m2
m1freq=dB(S(4,3))=14.774
6.000GHz
m2freq=dB(S(4,3))=1.930
9.000GHzm3freq=dB(S(2,1))=9.180
6.000GHz
m4freq=dB(S(2,1))=4.220
9.000GHz
Figure 5- 26 Comparison between LNA module -1 and -2. Solid line for LNA module -1 and star
line for module -2.
5.3 LNA Post-manufactured Simulation
LNA Module 2: with parasitic
Figure 5- 27 shows the simulation setup for post-manucactured simulation.
This is used for debugging the measurement result of implemented LNA module-2.
Component layout of via ground, inductance and capacitance are added in the Source
terminal of the FET and keeping other parameters constant The capacitor value is
swept from 1 pF to 100 pF and in the same time the inductor value is swept from 1
nH to 5 nH with small resistance (2 ohm). Figure 5- 28 shows the simulation result
with new arrangemet of parasistic effect in the source(S) terminal of the transistor.
Now there are some resonances at lower band. At 6.5 GHz with C=1pF and L=3nH
the power gain curve is same as LNA measurement gain curve but with higher
magnitude. In the simulation, it is also seen that at the higher value of capacitance the
gain curve is almost flat with higher magnitude. In the LNA measurement it was seen
by putting finger on the circuit. The gain increased and became more flat over the
band.
Module - 1
Module - 2
90
D10lay
D10lay _1
M odelTy pe=M W
GNDv i a
GNDv i a_1
M ode lTy pe=M W
GNDv ia
GNDv ia_2
M o delTy pe=M W
C
C3 5
C= Ca pF
Param Swe ep
Sweep2
Step=10
Stop=100
Start=1
Sim Ins tan c eNam e[6]=
Sim Ins tan c eNam e[5]=
Sim Ins tan c eNam e[4]=
Sim Ins tan c eNam e[3]=
Sim Ins tan c eNam e[2]=
Sim Ins tan c eNam e[1]="Sweep1"
SweepVar="Ca"
P ARAMETER SWEEP
Para m Sweep
Swe ep1
Step =1
Stop =5
Star t=1
Sim Ins tanc eNam e[ 6]=
Sim Ins tanc eNam e[ 5]=
Sim Ins tanc eNam e[ 4]=
Sim Ins tanc eNam e[ 3]=
Sim Ins tanc eNam e[ 2]=
Sim Ins tanc eNam e[ 1]="SP1"
Swe epVar="La"
PARAME TER SWEEPVAR
VAR5
Ra=2
Ca=1
La=1
EqnVar
C
C3 4
C= Ca pF
L
L1
R= Ra Ohm
L= La nH
L
L3
R=Ra Ohm
L=La nH
Term
Term 1
Z=50 Ohm
Num =1
Term
Term 2
Z=50 Ohm
Num = 2
V_DC
SRC2
Vdc =VGG V
VAR
VAR4
VGG=-0.17
EqnVar
s r_i m s _RC-I_0603_ G_19950814
R3
SM T _Pad="Pad2"
PART_NUM =RC-I-06 03-10R0-G 10 Ohm
V_DC
SRC3
Vdc =VDD V
VAR
VAR3
VDD=5
EqnVar
s r_im s _RC-I_0603_G_ 19950814
R4
SM T_Pad="Pad2"
PART_ NUM =RC-I-0603 -1500-G 150 Ohm
Te c hInc lude_NEC_ACTIVELIBRARY
NEC_ACTIVELIBRARY_Lib
Fi le=Nom inal
S_Param
SP1
Calc Nois e= y es
Step=0.1 GHz
Stop=9.5 GHz
Start=5.5 GHz
S-PARAMETERS
Options
Options 1
Tnom =25
Tem p=16. 85
OP TIONS
M ea s Eqn
m ea s 1Eqn
M eas
VAR
VAR1
Z0=50
EqnVar
SM T_Pad
Pad2
PO=0 m m
SM _Lay er="s older_m as k "
SM O=0.12 m m
PadLay er="b ond"
L=0.4 m m
W=0.55 m m
SMT_Pad
SM T_Pa d
Pad1
PO=0 m m
SM _Lay er="s older_m as k "
SM O=0.1 6 m m
PadLay e r="bond"
L=0.63 m m
W=0.55 m m
SMT_Pad
M SUB
M Sub1
Rough=0.00 1 m m
TanD=0.003 7
T=0.035 m m
Hu=1.0e+03 3 m m
Cond=5.8e7
M ur=1
Er=3.48
H=0.254 m m
MSub
S2P
SNP2
Ty pe =Touc hs tone
Fi le= "NE3512S02v 2 _2-18_2_20.s 2p "
21
R e f
s c _atc _ 100_CDR12BG_ B_19960828
C24
SM T_Pa d="Pad1"
PART_NUM =ATC100A3R0BP150 3pF
s c _atc _100_CDR12BG_B_1996 0828
C28
SM T_Pad="Pad1 "
PART_NUM =ATC100A3R0BP150 3pF
s c _atc _100 _CDR11BG_J _1 9960828
C26
SM T_Pad="Pad1"
PART_NUM = ATC100A100J CA150 10pF
s c _atc _1 00_CDR12BG_B_19960828
C27
SM T_Pad ="Pad1"
PART_NUM =ATC100A1R5 BP150 1.5pF
s c _atc _100_CDR12BG_B_19960828
C33
SM T_Pad="Pad1"
PART_ NUM =ATC100A1 R5BP150 1.5pF
s r_im s _RC-I_0603_ G_19950814
R6
SM T _Pad="Pad2"
PART _NUM =RC-I-060 3-3R90-G 3.9 Oh m
s c _atc _100_CDR11BG_J _1996 0828
C25
SM T_Pad="Pad 1"
PART_NUM =ATC100A101J CA15 0 100pF
s c _atc _100_CDR12BG_B_1996 0828
C31
SM T_Pad="Pad1 "
PART_NUM =ATC100A1R5BP150 1.5pF
s c _atc _100_CDR11BG_J _1996 0828
C29
SM T_Pad="Pad1 "
PART_NUM =ATC100A100J CA15 0 10pF
s c _atc _100_CDR11BG_J _19960 828
C3 0
SM T_Pad="Pad1"
PART_NUM =ATC1 00A101J CA150 100pF
s c _atc _100_CDR12BG_B_1996 0828
C32
SM T_Pad="Pad 1"
PART_NUM =ATC100A1R5BP150 1.5pF
Figure 5- 27 LNA post manufactured simulation
91
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
0
10
20
30
40
-10
50
Frequency GHz
Pow
er G
ain
dB(S
(2,1
))
m16
m17
m16freq=dB(S(2,1))=22.881Ca=1.000000, La=1.000000
7.000GHzm17freq=dB(S(2,1))=38.023Ca=1.000000, La=3.000000
6.500GHz
Figure 5- 28 Power gain vs frequency
5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.55.0 10.0
1
2
3
4
5
6
0
7
Frequency GHz
Nois
e F
igure
m18m19
m18freq=nf(2)=1.427Ca=1.000000, La=1.000000
6.500GHzm19freq=nf(2)=0.892Ca=100.000000, La=5.000000
6.500GHz
Figure 5- 29 Noise figure
92
6 Conclusion and Further work
The designed LNA shows good gain but over a narrower bandwidth than the
desired specifications. This can be explained by grounded-source parasitic effects.
Post-manufactured simulations were done in order to identify the origin of the
problem. The post-manufactured simulations were done by replacing ideal ground of
the FET source terminal with the layout component of grounded-via. Moreover in
order to add more parasitic effects, additionally inductor and capacitor were also
added. The capacitor value is swept from 1 pF to 100 pF and in the same time the
inductance value is swept from 1 nH to 5 nH with small resistance (2 ohm). Some
resonances at lower band were identified. At 6.5 GHz with C=1pF and L=3nH the
gain curve is same as LNA measurement gain curve but with higher magnitude. In
the simulation, it was also seen that at the higher value of capacitance the gain curve
is almost flat with higher magnitude.
In conclusion, from the post-manufactured simulations, it can be assumed that
transistor’s source terminal was not properly grounded. It is also known that at the
RF/MW frequency the lumped elements behavior is quite different from that at low-
frequency and we can conclude now that accurate capacitor and inductor S-
parameters models should also be used, when they are available. A better option is to
implement, whenever it is possible, passive components using transmission lines that
will behave like passive components, e.g. Capacitors, inductors. These components
can be implemented by carefully choosing the transmission line characteristics
impedance (Z0) and line length line length (l) and then, by accurate simulation using
electromagnetic simulations as Momentum in ADS.
Future work for this thesis is at first manufacture the next prototype in a better
process with smaller via holes and better process accuracy.
93
Appendix
1. Lists of S-parameters data of NE3512S02 Hetero-junction FET at different
frequencies are given below. These data are obtained from the manufacturer data file,
NE3512S02v2_2-18_2_20.s2p
2. Lists of minimum noise figure (Fmin) of NE3512S02 Hetero-junction FET at
different frequencies are given below. These data are also obtained from the
manufacturer data file, NE3512S02v2_2-18_2_20.s2p
94