4. ENCODING AND DECODING SYSTEM FOR A CYCLIC ONE ERROR CORRECTING CODE

4.1 OBJECT OF THE LABORATORY In this laboratory work we shall refer to an encoding and decoding system for a cyclic one error correcting code. 4.2 THEORETICAL APPROACH The word of a cyclic code can be represented under a polynomial form:

where the n coefficients ai∈{0,1} represents the bits of the code word: m information bits and k =n-m control bits; n=2k-1 for the one error correcting code. A cyclic code is defined by its generator polynomial g(x) of degree k. The code words of a cyclic code generated by g(x) are also polynomials of degree n-1, being multiples of g(x). Therefor, any cyclic code word v(x) can be divided by g(x). This property of the cyclic code words is used in the encoding and decoding. Being given the information bits and using the property by which a code word v(x) divided by g(x) gives a null reminder, the control bits can be determined. At decoding, it is verified if the received word v’(x) divided by g(x) also gives a null reminder. If the reminder is zero we have a correct code word, else the received word is an erroneous one. In the second case, if the structure of the encoder allows the correction of the errors, the error word ε(x) will be determinate and the correct word will be: v(x)=v’(x)+ ε(x) (4.2) We consider a systematic cyclic code with n=7, k=3, m=4 having the following structure of the words:

v(x)=a6x6 + a5x5 + a4x4+…+ a1x + a0 where a6, a5, a4, a3 are the information bits and a2, a1, a0 are the control bits. With this code can be transmitted N messages (2m=16≥N) and can be corrected e=1 errors. As generator polynomial g(x) = x3 +g2x2 + g1x + 1 can be chosen gb(x) = x3 +x +1 (g2 = 0) or ga(x) = x3 +x2 +1 (g1 = 0). The polynomial divider circuit designed with a linear feedback shift register (fig. 4.1) can encode and decode the words of a cyclic code generated by g(x).

Fig 4.1

(4.1) axaxaxav(x) 012-n

2-n1-n

1-n++++= L

C2, C1, C0 are the three cells of the shift register, gi∈{0,1} are multiplication constants and ⊕ represent modulo-two summators which realize the feedback reaction. The characteristic matrix T defined for this circuit is the following:

which allows for the states of the register to be determinated.

The state of the register at the moment i is given by the relation: The circuit divides the polynomials v(x) applied at the input A by g(x), meaning that after

applying the succession of the symbols a6 a5 … a1 a0, the cells C2, C1, C0 represent a modified form of the reminder. The final states of the register cells are null only when the reminder is zero. At encoding, the circuit has the following operation: in the first four periods of the clock at the input A are applied the known bits, the information bits: a6, a5, a4, a3; in the next three periods of the clock at the inputs A and B of the summator S1 are applied the same signals (the input A is connected with the input B), respectively the ones from the output of the summator S2. Therefor, the final state of the register, S7, is null. The reminder of the division of the word v(x) by g(x), applied at the input A, is also null, meaning that the succession of symbols applied at the input A are the bits of a cyclic code word. In point A are obtained the control bits a2, a1, a0 of the code word which has a6, a5, a4, a3 as information bits. The encoding operation is made in seven periods of the clock. Next, the relations between the information and the control bits are obtained by writing the succession of the feedback shift register states based on the characteristic matrix. For g(x) = x3 + x + 1, which chosen as the generator polynomial, we have:

(4.3) g g g

1 0 00 1 0

T

210

=

. 100

Uandk cell theof state for the Cst ,register theof state afor Cst Cst Cst

S :denoted Are k

2

1

0

=

=

(4.4) Ua STS i1-ii+=

.0S state initial The 0 =

=

0 1 11 0 00 1 0

T

Using the relation (4.4), we obtain:

Taking into consideration the fact that after seven periods of the clock the state of the shift register is the null one and based on (4.11), the relation between the information and the control bits can be obtained:

with a2 = a5 +a4 +a6 .

(4.7) UaUTa UTa aa

aa

UaSTS

(4.6) Ua UTa aa0

UaSTS

(4.5) a00

UaS

452

6

46

5

6

423

56

5

6512

6

61

++=

+=+=

+=

=+=

==

(4.10) UaUTa

UTa UTaUTa UTa aaaaaaaa

aaaUaSTS

12

23

34

45

56

1543

2356

356

156

++

++++=

+++

+++++

=+=

(4.11) UaUTaUTa

UTa UTaUTa UTa aaaaaaaaaaaa

UaSTS

012

2

33

44

55

66

0432

1543

2356

067

+++

++++=

+++++++++

=+=

(4.12) aaaaaaaaaaaa

:so and 000

S

6530

5431

4652

7

++=++=++=

=

(4.9) Ua UTa UTaUTa UTa aaaa

aaaaa

UaSTS 232

43

54

6

2356

356

46

245 ++++=

+++++

+=+=

(4.8) Ua UTaUTa UTa aaa

aaa

UaSTS 342

53

6

356

46

5

334 +++=

+++=+=

Applying the same procedure for g(x) = x3 + x2 + 1, the resulting relations between the information and the control bits are the next ones:

It can be demonstrated that the expression given by the relation (4.11) can be written as: where:

is the control matrix of the encoder and the code word v can be represented as a matrix with one row:

At decoding, at the input A are applied successively the bits of the received word : a6’, a5’… a1’, a0’, based on (4.11) the state of the register becomes:

Taking in consideration (4.14), is obtained:

Therefor, after the bits of the received word were introduced, the state of the register is in fact the syndrome. If all the bits ak’ are correct, then S7 = z = 0. If one of the bits ak’ is erroneous, then S7 = z ≠ 0. Let ai’ be the erroneous bit :

The relation (4.18) becomes:

for any erroneous position, so for any error word there is a different syndrome, therefor this code has properties for correction. For the determination of the error word corresponding to the syndrome, the register must have a free evolution for the next seven periods of the clock. Therefor, to be able to make the correction of a 7 bits word there are necessary 14 periods of the clock, the next code word being introduce for correction in a second divider circuit, which will operate in push-full with the first one.

`

(4.13) aaaaaaaaaaaa

5430

6541

6432

++=++=++=

(4.14) v HS T

7=

[ ] (4.15) UT UT UT UT UT UT UH 65432=

[ ] (4.16) a a a a a a av 6543210=

(4.17) U'aUT'aUT'aUT'aUT'aUT'aUT'aS 012

23

34

45

56

67++++++=

(4.18) z 'v HS T7

==

(4.19) ikfor 1a'a

61, 0, k with ikfor a'a

k k

k k

=+==≠= K

(4.20) UTUTUaUTaUTaUTaz ii01

55

66 =+++++= L

The register states in the its free evolution can be obtained with the following relations:

4.3 PRESENTATION OF THE LABORATORY PATTERN The block scheme is presented in figure 4.2 and is composed by the encoder, the noisy channel simulator, the decoder, the clock generator common for the encoder and the decoder. The encoder contains a shift register with 7 cells, connected in a ring, through which a unit passes in the rhythm of the clock generated by the clock generator GT, the encoder register with the cells C2, C1, C0 having the feedback implemented with the modulo-two summators S1 and S2 and the gates SAU1, SAU2, SI1, SAU3 . The generator polynomial can be chosen with the K1 switches. With both switches on: g(x)=ga(x) = x3 +x2 +1 and with both switches off: g(x)=gb(x) = x3 +x +1. The information bits can be 0 or 1 depending on the outputs of the R 1 cells 1, 2, 3, 4 if they are in short-circuit or not. At the output of R1 are obtained in the first four periods of the clocks the information bits a6, a5, a4, a3 which are applied through SAU3 at the input A of the summator S1. In the next three periods of the clock, when at the output of the circuit SAU1 are obtained only zeroes, at the output of the circuit SAU2 is obtained a signal with 1 logic level marking the presence of the control bits. This signal opens the gate SI1 allowing the control bits to pass from the output B of the summator S2 through SAU3 in the point A. In this time interval the signals from A and B are identical. In A is obtained the succession of bits a6 a5 a4 a3 a2 a1 a0 of the code word.

IT

(4.21)

001

UTUTTS

UTTSTS

UTTSTS

7

1-i1-i-7i114

i2

89

i

78

=

=⋅=

⋅=⋅=

⋅=⋅=

−−

M

(4.2). correction themake toand (x) error word thefind toallowswhich

recognized is state This . 001

state fixed in the goesregister theposition) erroneous on the

dependsch moment whi a(in tact theof period 1-i-14 in the ,a isbit erroneous theIf i

ε

Fig. 4.2 The noisy channel is simulated with the modulo-two summator S3 and the gate SAU4, which allows for the errors to be applied on the desired positions by short-circuiting the corresponding inputs of SAU4 with the corresponding cells of the register R1. Errors can be also applied from an external source. The decoder contains the memory register R2 , two decoding circuits, decoder 1 and decoder 2 operating in push-full, because there are necessary 14 clock for an error to be found, a switch K2 which allows the access of the odd words to the first decoder and the access of the even words to the second one and the correction circuit implemented with the modulo-two summator S4. The first received code word is simultaneously introduced in the main register R2 and through the switch K2 in the decoder 1. After seven periods of the clock the word is entirely loaded and in the decoder 1 there is the corresponding syndrome for the received word. In the next seven periods of the clock the previous word is evacuated bit by bit from register R2 and the next word is loaded bit by bit which is also loaded in the decoder 2, decoder 1 having a free evolution. When the erroneous bit is in the last cell of R2, the decoder 1 is in the state:

The fixed state detector (001) recognize this state, providing through SI2 and SAU5 the impulse for correction. This impulse is the error word ε(x) in the single error case, the correction being realized in SI4 as in relation (4.2). The correct word is present at the output of the summator S4. The circuit SI2 allows for the correction impulse to be applied only in the time interval when the decoder 1 has a free evolution for avoiding a state [001], which appears during the time when the decoder 1 is receiving the bits of the word v’(x), to be interpreted as a correction impulse. Figure 4.3 represents the block scheme of the decoder and of the noisy channel.

=⋅=−−

001

UTUTTS 1-i1-i-7i114

ENCODER DECODER

DECODER 2

DECODER 1

CHANNEL

The circuits SAU1, SAU2, SAU4 from the block scheme are implemented with the gates SI-NU 1, 2, 3, 4.

as inputs the inverted outputs (1, 2, 3, 4, 5, 6, 7) of the register R1 cells. The circuit SI1 implemented with the gates SI-NU 6 and 8, and the circuit SAU3 with the gates SI-NU 3,5,7. The logic scheme of the decoder is given in figure 4.4. The switch K2 is designed with CBB1 and the gates 9, 10, 11, 12 . CBB1 is a J-K flip-flop its input T being the inverted output of the cell 1 from R1. During 7 periods of the clock CBB1 remains in the state 1 and through the gates 9 and 10 the received word enters in decoder 1, during other 7 periods of the clock CBB1 remains in the state 0 and the next received word enters through the gates 11 and 12 in decoder 2. The role of the fixed state detector 001and of the circuit SI2 is accomplished by the gate13 and at its output is obtained the inverted correction impulse of decoder 1. The circuit SAU5 is implemented with the gate 14, which has at its output the correction impulse for the both decoders. With the help of the circuit CBB2 operating as D cell, the tilting mono-stable circuit CBM and the gate 15 bring to 0 the cells of the feedback register of the decoder 1. In a similar way is acted for the decoder 2.

have SAU ,SAU,SAU circuits thebabarelation ion theconsideratin Taking 421⋅=∪

Fig. 4.3

Fig.4.4 4.4 LABORATORY WORK OPERATIONS ORDER 1. Study the operation of the pattern on the scheme block and on the logic scheme. 2. Supply the pattern, choose the generator polynomial g(x) with the switch K1 and start

the time base of the synchro-scope with the rising front of the signal from the switch K2 (21).

3. Choose the information bits, and calculate the control bits depending on g(x) chosen with the relation (4.12) or (4.13).

4. Visualize the clock signal (8) and the signals from the inverted outputs of the R1 cells: (1) (2) (3) (4) (5) (6) (7).

5. Visualize the information bits (10), the signal signals the position of the control bits

(9), the control bits (11) and the code word (12). 6. Use the relations (4.5) – (4.11) to determine the succession of the encoder register

states and verify the succession of the cell C0 states (13) of this register (for g(x)= x3+x2+1 calculate the states of the register).

7. Choose an error word with only one unit and visualize the error word (14) and the erroneous one (15). 8. Visualize the erroneous word from the output of R2 (16). 9. For the erroneous bit ai, determine with the relations (4.4) – (4.11) the succession of the register states during 14 periods of the clock, replacing ai with ai+1 (for g(x)= x3 + x2 + 1) (see 6) for the first 7 periods of the clock and next with the relations (4.21). Verify the passing through the state (001) of the register in the 14-i-1 period of the clock by visualizing the signal from the output of the cell C0 of the first decoder. 10. Visualize the inverted correction signal of the first encoder (18) and the correction signals of the two decoders (19). 11. Visualize the corrected code word (20). 4.5 QUESTIONS 1. For a g(x) calculate the control polynomial h(x)= xn + 1/g(x) and determine the matrix H:

Verify that it is the same with the one given by the relation (4.15). 2. What will happen if the received word is erroneous on more than one position?

=

0 0 h h h h 00 h h h h h 0

h h h h h 0 0H

0123

01234

01234