38226967 arm cortex m0 overview

ARM Cortex-M0 OverviewBy: Daniel Widyanto

September 2010

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Contents

Introduction to ARM Cortex-M0

Programmer’s Model : Processor Modes

Programmer’s Model : Stacks

Programmer’s Model : Core Registers

Programmer’s Model : Interrupts and Exceptions

Quizzes

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ARM Cortex-M0:– Entry-level 32-bit ARM Cortex processor designed for a broad range of embedded

applications

Benefits:– simple, easy-to-use programmers model– highly efficient ultra-low power operation– excellent code density– deterministic, high-performance interrupt handling– upward compatibility with the rest of the Cortex-M processor family

Cortex-M0 core peripherals– NVIC:

• An embedded interrupt controller that supports low latency interrupt processing.– System Control Block:

• Provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

– Optional system timer (SysTick): • A 24-bit count-down timer. If implemented, use this as a Real Time Operating System (RTOS) tick

timer or as a simple counter

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Introduction to ARM Cortex-M0 (cont’d)

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Programmer’s Model

Processor Modes

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Programmer’s ModelProcessor Modes

Thread mode – Used to execute application software. The processor enters Thread mode when it

comes out of reset.

Handler mode – Used to handle exceptions. The processor returns to Thread mode when it has

finished all exception processing.

Note:Other ARM architectures support the concept of privileged or unprivileged software execution. This processor does not support different privilege levels. Software execution is always privileged, meaning software can access all the features of the processor.

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Stacks

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Programmer’s ModelStacks

Full descending: stack pointer indicates the last stacked item on the stack memory.

Two stacks, two independent stack pointers:

– Handler mode always uses the MSP (Main Stack Pointer)– Thread mode can use MSP (Main Stack Pointer) by default, or PSP (Process Stack

Pointer)• Controlled by CONTROL register

In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

Processor mode Used to execute Stack used

Thread Applications Main stack or process stack

Handler Exception handlers Main stack

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Core Registers

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Programmer’s ModelCore Registers

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Program Status Register (PSR) combines:– Application Program Status Register (APSR)– Interrupt Program Status Register (IPSR)– Execution Program Status Register (EPSR)

• Mutually exclusive each other.• User can access the whole registers as ‘PSR’, or individual blocks as ‘APSR’ / ‘IPSR’ /

‘EPSR’, or combination of two blocks

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Interrupt and Exceptions

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Programmer’s ModelInterrupts and Exceptions

The vector table is fixed at address 0x00000000

1st record is stack address for MSP

The rest of the record are addresses for exception handlers

– Address only. No instruction such as ‘branch <int_handler>’

Address for exception handlers must be in ‘odd’ value, since ARM Cortex-M0 only supports Thumb mode

– Bit[0] in address determined whether Thumb mode is used or not

HardFault exception will be triggered for ‘even’ address.

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Exception entry– ARM Cortex-M0 is automatically save the registers into stack (pointed by MSP)

before executing exception handler

– The exception handler address then fetch and executed

Exception return– Use ‘BX LR’ to return the registers value from stack– LR defines the mode and stack pointer for the return address:

• LR = 0xFFFFFFF1: Return to Handler mode, use MSP after return• LR = 0xFFFFFFF9: Return to Thread mode, use MSP after return• LR = 0xFFFFFFFD: Return to Thread mode, use PSP after return

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Definition:– An event that alters the normal sequence of execution

Unconfigureable priority exceptions are un-maskable. Configurable priority exceptions are maskable (using ‘PRIMASK’)

Priority value is 0 (highest) to 192 (lowest)– Default priority is 0 (highest)– For IRQ0-IRQ31, priority is handled by IPR0 – IPR7 register– For SVCall, SysTick, and PendSV, priority is handled by SHPR2 – SHPR3 register

Configurable Priority Unconfigureable Priority

Synchronous SVCall HardFault

Asynchronous PendSV, SysTick, IRQ0-IRQ31

Reset, NMI

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Magic words:– Tail-chaining

• On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.

• Happens if the later interrupt has same or lower priority

– Late-arriving• If a higher priority exception occurs during state saving for a previous exception, the

processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved would be the same for both exceptions. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.

• Happens if the later interrupt has higher priority

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IRQ[31:0]

NVIC: Connecting external peripherals to the core

IRQ Mask*

S R

IRQ Pending

S R

Prioritize CPU

ICERISER

*) Mask active means interrupt is enabled

ICPRISPR

IPR0-IPR7

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Quizzes

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Quizzes

Run ‘LPCXpresso’ and download ‘CMSIS’ example

Open ‘core_cm0.h’ and ‘core_cm0.c’ file

Answer these questions:– What assembly instruction that is needed to enable interrupts ? – How to set MSP ? (clue: C function name)– How to enable specific IRQ ? (clue: C function name)– How to set the IRQ priority ? (clue: C function name)

1

ARM Cortex-M0 OverviewBy: Daniel Widyanto

September 2010

2

Contents


Programmer’s Model : Processor Modes

Programmer’s Model : Stacks

Programmer’s Model : Core Registers

Programmer’s Model : Interrupts and Exceptions

Quizzes

3


4

4


ARM Cortex-M0:– Entry-level 32-bit ARM Cortex processor designed for a broad range of embedded

applications

Benefits:– simple, easy-to-use programmers model– highly efficient ultra-low power operation– excellent code density– deterministic, high-performance interrupt handling– upward compatibility with the rest of the Cortex-M processor family

Cortex-M0 core peripherals– NVIC:

• An embedded interrupt controller that supports low latency interrupt processing.– System Control Block:

• Provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

– Optional system timer (SysTick): • A 24-bit count-down timer. If implemented, use this as a Real Time Operating System (RTOS) tick

timer or as a simple counter

ARM Cortex-M0 have extra peripherals, other than its processing unit core:-NVIC: To control the interrupt-WIC: Wakeup interrupt controller, to wake the MCU from power saving mode without any clock-SysTick: Simple 24-bits timer. This timer can be used as RTOS timer to make the RTOS portable for all of ARM Cortex-M series (Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4)-Serial Wire Debug (SWD): To enable simple external connection to debug and trace ARM Cortex-M series

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5

Introduction to ARM Cortex-M0 (cont’d)

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Processor Modes

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Programmer’s ModelProcessor Modes

Thread mode – Used to execute application software. The processor enters Thread mode when it

comes out of reset.

Handler mode – Used to handle exceptions. The processor returns to Thread mode when it has

finished all exception processing.

Note:Other ARM architectures support the concept of privileged or unprivileged software execution. This processor does not support different privilege levels. Software execution is always privileged, meaning software can access all the features of the processor.

For other ARM Cortex-M series (except ARM CortexM0), the ‘unprivileged’ mode:• has limited access to the MSR and MRS instructions, and cannot use the CPS instruction• cannot access the system timer, NVIC, or system control block• might have restricted access to memory or peripherals.

The ‘Handler’ mode is always privileged. The ‘Thread’ mode can be privileged or unprivileged, depending on the settings at ‘CONTROL’ register.

ARM Cortex-M0 retain the mode for compatibility with other ARM Cortex-M series.

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Stacks

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Programmer’s ModelStacks

Full descending: stack pointer indicates the last stacked item on the stack memory.

Two stacks, two independent stack pointers:

– Handler mode always uses the MSP (Main Stack Pointer)– Thread mode can use MSP (Main Stack Pointer) by default, or PSP (Process Stack

Pointer)• Controlled by CONTROL register

In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

Processor mode Used to execute Stack used

Thread Applications Main stack or process stack

Handler Exception handlers Main stack

• The ’MSP’ and ’PSP’ are usually used in RTOS to differentiate application and kernel codes. • To simplify the firmware, in ARM Cortex-M0, the ’PSP’ can be ignored. User can always use ’MSP’ for all of their interrupt handling or normal codes.• On reset, the processor loads the ’MSP’ with the value from address 0x00000000.

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Core Registers

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Notes:• Some ARM Cortex-M series instruction only works with ‘low registers’ (R0-R7), specially the memory access instructions• The PRIMASK register prevents activation of all exceptions with configurable priority. The bit assignments are:

Bits Name Function[31:1] - Reserved[0] PRIMASK

0 = no effect1 = prevents the activation of all exceptions with configurable priority.

• The CONTROL register controls the stack used when the processor is in Thread mode. The bit assignments are:

Bits Name Function[31:2] - Reserved[1] Active stack Defines the current stack:

pointer 0 = MSP is the current stack pointer1 = PSP is the current stack pointer.In Handler mode this bit reads as zeroand ignores writes.

[0] - Reserved.

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Program Status Register (PSR) combines:– Application Program Status Register (APSR)– Interrupt Program Status Register (IPSR)– Execution Program Status Register (EPSR)

• Mutually exclusive each other.• User can access the whole registers as ‘PSR’, or individual blocks as ‘APSR’ / ‘IPSR’ /

‘EPSR’, or combination of two blocks

•User can also access combination of the two blocks:Register CombinationPSR APSR, EPSR, and IPSRIEPSR EPSR and IPSRIAPSR APSR and IPSREAPSR APSR and EPSR

•APSR bit assignments:Bits Name Function[31] N Negative flag[30] Z Zero flag[29] C Carry or borrow flag[28] V Overflow flag[27:0] - Reserved

•IPSR bit assignments:Bits Name Function[31:6] - Reserved[5:0] Exception number This is the number of the current exception0 = Thread mode

1 = Reserved2 = NMI3 = HardFault4-10 = Reserved11 = SVCall12, 13 = Reserved14 = PendSV15 = SysTick, if implemented[a]16 = IRQ0n+15 = IRQ(n-1)[b](n+16) to 63 = Reserved.

[a] If the device does not implement the SysTick timer, exception number 15 is reserved.[b] The number of interrupts, n, is implementation-defined, in the range 1-32.

•EPSR bit assignmentsBits Name Function[31:25] - Reserved[24] T Thumb state bit[23:0] - Reserved

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Interrupt and Exceptions

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The vector table is fixed at address 0x00000000

1st record is stack address for MSP

The rest of the record are addresses for exception handlers

– Address only. No instruction such as ‘branch <int_handler>’

Address for exception handlers must be in ‘odd’ value, since ARM Cortex-M0 only supports Thumb mode

– Bit[0] in address determined whether Thumb mode is used or not

HardFault exception will be triggered for ‘even’ address.

• Other ARM Cortex-M series supports vector address remapping / relocation. ARM Cortex-M0 only support address 0x00 as vector table base.

• Bit[0] in address determined whether the CPU should use Thumb mode or not. It’s part of ARM7TDMI compatibility.

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Exception entry– ARM Cortex-M0 is automatically save the registers into stack (pointed by MSP)

before executing exception handler

– The exception handler address then fetch and executed

Exception return– Use ‘BX LR’ to return the registers value from stack– LR defines the mode and stack pointer for the return address:

• LR = 0xFFFFFFF1: Return to Handler mode, use MSP after return• LR = 0xFFFFFFF9: Return to Thread mode, use MSP after return• LR = 0xFFFFFFFD: Return to Thread mode, use PSP after return

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Definition:– An event that alters the normal sequence of execution

Unconfigureable priority exceptions are un-maskable. Configurable priority exceptions are maskable (using ‘PRIMASK’)

Priority value is 0 (highest) to 192 (lowest)– Default priority is 0 (highest)– For IRQ0-IRQ31, priority is handled by IPR0 – IPR7 register– For SVCall, SysTick, and PendSV, priority is handled by SHPR2 – SHPR3 register

Configurable Priority Unconfigureable Priority

Synchronous SVCall HardFault

Asynchronous PendSV, SysTick, IRQ0-IRQ31

Reset, NMI

• ResetInvoked on power up or a warm reset. • Non-Maskable Interrupt (NMI)Asserted if NMI pin is pulled HIGH by external circuitry. Not implemented in LPC111x• HardFaultOccurs because of an error during normal or exception processing (eg. Un-aligned memory access)• SVCallException that is triggered by the ‘SVC’ instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.• PendSVInterrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. Invoked by setting ’PENDSVSET’ bit in ‘ICSR’.• SysTickException when the system timer reaches zero. • Interrupt (IRQ)Exception signaled by a peripheral, or generated by a software request.

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Magic words:– Tail-chaining

• On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.

• Happens if the later interrupt has same or lower priority

– Late-arriving• If a higher priority exception occurs during state saving for a previous exception, the

processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved would be the same for both exceptions. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.

• Happens if the later interrupt has higher priority

Question: What it takes to enable the tail chaining / late arriving feature ?Answer: Nothing. It’s enabled by hardware by default.

Question: How to disable the tail-chaining / late-arriving feature ?Answer: Disable the ‘configurable exceptions’ through PRIMASK. The Reset, NMI, and HardFault cannot be disabled.

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IRQ[31:0]

NVIC: Connecting external peripherals to the core

IRQ Mask*

S R

IRQ Pending

S R

Prioritize CPU

ICERISER

*) Mask active means interrupt is enabled

ICPRISPR

IPR0-IPR7

19

Quizzes

20

Quizzes

Run ‘LPCXpresso’ and download ‘CMSIS’ example

Open ‘core_cm0.h’ and ‘core_cm0.c’ file

Answer these questions:– What assembly instruction that is needed to enable interrupts ? – How to set MSP ? (clue: C function name)– How to enable specific IRQ ? (clue: C function name)– How to set the IRQ priority ? (clue: C function name)

38226967 arm cortex m0 overview

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