Cortex-M4

Dariusz Chaberski

STM32 Cortex-M4 implementation

2

Processor core registers

3

APSR, IPSR, EPSR and PSR bit assignments

ICI - Interruptible-continuable instructions (LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, VPOP)

IT - If-Then block

4

Load and Store Multiple instructions

5

Condition Flags - Example

6

Memory map

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Bit-band mapping

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Exception model

9

Vector table

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Cortex-M4 stack frame layout

11

Condition code suffixes

12

Condition code suffixes - continued

13

Instruction width selection

14

Basic structure of a five-volt tolerant I/O port bit

15

Port bit configuration table

GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF =alternate function

16

Port bit configuration table

17

DMA block diagram

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Channel selection

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EXTI block diagram

20

Single ADC block diagram

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Single ADC block diagram

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Timing diagram

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Data alignment of 12-bit data

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Left alignment of 6-bit data

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Multi ADC block diagram

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Multi ADC block diagram

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DAC channel block diagram

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Noise generation

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DAC conversion (SW trigger enabled) with triangle wavegeneration

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Digital camera interface

31

DCMI signal waveforms

32

Advanced-control timers (TIM1&TIM8)

33

Addressing Mode 1 - Data-processing operands

{}{S} , ,

+ #

immed_8 == 0x3F, rotate_imm == 0xE

immed_8 == 0xFC, rotate_imm == 0xF

+

+ , LSL #

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Addressing Mode 1 - Data-processing operands

{}{S} , ,

+ , LSL

+ , LSR #

+ , LSR

+ , ASR #

+ , ASR

+ , ROR #

+ , ROR

+ , RRX

35

Addressing Mode 2 - Load and Store Word or Unsigned Byte

LDR|STR{}{B}{T} ,

+ [, #+/-]

+ [, +/-]

+ [, +/-, #]

[, +/-, LSL #]

[, +/-, LSR #]

[, +/-, ASR #]

[, +/-, ROR #]

[, +/-, RRX]

36

Addressing Mode 2 - Load and Store Word or Unsigned Byte

LDR|STR{}{B}{T} ,

+ [, #+/-]!

+ [, +/-]!

+ [, +/-, #]!

+ [], #+/-

+ [], +/-

+ [], +/-, #

37

Addressing Mode 3 - Miscellaneous Loads and Stores

LDR|STR{}H|SH|SB|D ,

+ [, #+/-]

+ [, +/-]

+ [, #+/-]!

+ [, +/-]!

+ [], #+/-

+ [], +/-

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Addressing Mode 4 - Load and Store Multiple

LDM|STM{} {!}, {^}

+ IA (Increment After)

+ IB (Increment Before)

+ DA (Decrement After)

+ DB (Decrement Before)

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Addressing Mode 5 - Load and Store Coprocessor

{}{L} ,,

+ [,#+/-*4]

+ [,#+/-*4]!

+ [],#+/-*4

+ [],

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ARM Instructions

ADC{}{S} , ,

ADDS R4,R0,R2ADCS R5,R1,R3

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ARM Instructions

AND{}{S} , ,

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ARM Instructions

B{L}{}

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ARM Instructions

BIC{}{S} , ,

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ARM Instructions

BLX

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ARM Instructions

BLX{}

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ARM Instructions

CDP{} , , , , , CDP2 , , , , ,

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ARM Instructions

CLZ{} ,

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ARM Instructions

LDC{}{L} , , LDC2{L} , ,

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ARM Instructions

MLA{}{S} , , ,

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ARM Instructions

QADD{} , ,

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Thumb Instructions

ADC ,

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Thumb Instructions

Rd = Rn + immed_3

Rd = Rd + immed_8

Rd = Rn + Rm

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Thumb Instructions

Rd = Rd + Rm

Rd = (PC AND 0xFFFFFFFC) + (immed_8 * 4)

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Thumb Instructions

Rd = SP + (immed_8

Thumb Instructions

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