3 objectives student name: ajao hazzan id: 073902078 [email protected] kuala lumpur...
TRANSCRIPT
Student Name: Ajao Hazzan ID: 073902078
[email protected] Lumpur Infrastructure University College
STUDY AND ANALYSIS OF WIRE BONDWIDTH CONTROL FOR IC DESIGN
This project focuses primarily on wire bond control and it explains extensively some of the factors that contributes to yield loss and how it could be controlled so that semiconductor and microelectronics companies can meet their goals and monetary profit plan. The Figure Below show the picture of a device after wire bonding process.
The objective of this project is to make known the technical process of wire bonding and some of the factors causing bonding failure. 1.To solve wire bond problems2.To reduce yield loss related wire bond issue3.To show the process of IC fabrication.
Fabrication Process
Start
Choose Machine
Set Up Parameter
MeasureBond width
Good Production
End
Yes
No
Wire Lot and Wedge Number
Run Production
Figure 4 shows the flow chart of the process it explain the step by step method implemented in solving the wire bond problems.To observe the bond width variation by time series on one particular machine running the Same device and production lot.
Parameters settingPower Time Force Bond Width(Mils)
1st 2nd 1st 2nd 1st 2nd 1st 2nd
95 85 50 45 5 5 4.6 4.495 85 50 45 5 5 5 4.3
95 85 50 45 5 5 4.2 4.395 85 50 45 5 5 4.2 4.295 85 50 45 5 5 4.6 4.295 85 50 45 5 5 4.8 4.2
Ave:4.6 Ave:4.4Delta: 0.2 Mils
Parameters SettingPower Time Force Bond Width(mils)
1st 2nd 1st 2nd 1st 2nd 1st 2nd
95 80 45 45 5 3 3.9 2.695 80 45 45 5 3 3.3 2.795 80 45 45 5 3 3.3 2.595 80 45 45 5 3 3.5 2.8
Ave:3.5 Ave:2.65Delta: 0.85Mils
Since the world is heading towards nanotechnology engineers and researchers should begin to look for a better means of providing interconnection in fabrication of these various ICs we have today without using bonding machine. I would suggest by designing the PCB layout of the wire interconnection path and by using photonic wire-laser to provide the interconnection among the various terminals or metallic electron diffusion the interconnection could be made possible for the signal to flow from one point of the device to the other.
There are lots of factors which contribute to yield loss and many of it are tied to incurrent or wrongful parameters setup for the machines, bonded surface contaminants, bond geometry, take off angle, loop height, pattern recognition, trend to ceramic, ultimate tensile strength, Increased bond adhesion and pull test results, lower temperature and reduced ultrasonic power, parameters for bond-wire design within the range.
If process engineers carefully monitors all these factors mentioned and follows the method proposed in this project wire bond failure and rejects units which reduces most manufacturing companies’ profits and progress will ultimately be reduced.
Project Supervisor: Anwar H. Ibrahim
Project Presenter: Ajao Hazzan ID: [email protected]
Figure 1: K$&S Bonder
The Figure 1 below show the Picture of the bonding machine use at the production floor
The in Figure 2 is the measuring tool called TM scope, is used for collection of data by measuring the bonding terminals.
Figure 2:The TM Scope
Figure 3 : Bond Width Spec.
Figure 4:The TM Scope
The table 1 below show s the good example of what the bond width value range should be.
The table 1
Most Important
The Graph show s Good
Result
The table 2
The table 2 below shows an example of poor bondwidth data . The data are below the minimum and maximum specification.
The Graph show s Good Result
8 AcknowledgementI really want to thank Freescale semiconductor Malaysia for given me the opportunity to carry out this research work in their company and for all their supports. I am indeed grateful to the management and all my field supervisors. Thanks to you all
Figure 4: Pictures at clean room
The Figure 1 : Device Picture after wire Bonding