13-1 ee 319k introduction to microcontrollers lecture 13: serial communications interface (sci),...

13-1

EE 319KIntroduction to Microcontrollers

Lecture 13: Serial Communications Interface (SCI), Producer-Consumer problems,

FIFO Queues, Lab9

Read Book Sections 8.1, 8.2, 12.3.2, 12.3.3, 12.4

13-2Ramesh Yerraballi

Serial Comm. Interface (SCI)

This protocol is also known as UART (Universal Asynchronous, Receiver Transmitter)

Originally used to connect i/o terminals to mainframes.

Neither fast nor reliable but simple

SCI Device Driver Public routines

SCI1_Init SCI1_InChar SCI1_OutChar

Private Objects SCI1CR2 SCI1BD SCI1SR1 SCI1DRL


SCI Basics

Baud Rate: The total number of bits transmitted per secondbaud-rate = 1/bit-time

Mode Bit (M): Selects 8-bit(M=0) or 9-bit (M=1) data frames

5V0Vb0 b1 b2 b3 b4 b5 b6serial port b7

one framestart stop

Frame: The smallest complete unit of serial transmission.

Bandwidth: The amount actual information transmitted per second.

A serial data frame with M=0

number of information bits/frame Total number of bits/frame

x baud-rateBandwidth =


Transmitting in Asynchronous Mode

The software writes to SCI1DRL, then 8 bits of data are moved to the shift register start and stop bits are added shifts in 10 bits of data one at a time on TxD line shift one bit per bit time (=1/baudRate)

SCI0DRLwrite data

1 T8 0stop start

shiftclock data TxD7 6 5 4 3 2 1 0

9S12C329S12DP5129S12DP512orPS1PS3PS1

transmit data registerData and shift registers implement the serial transmission


Receiving in Asynchronous Mode

The receiver waits for the 1 to 0 edge signifying a start bit, then shifts in 10 bits of data one at a time from RxD line shift one bit per bit time (=1/baudRate) start and stop bits are removed checked for noise and framing errors 8 bits of data are loaded into the SCIDRL

Data and shift registers implement the receive serial interface

SCI0DRLread data

1 R8 0stop start

shiftclock data RxD7 6 5 4 3 2 1 0

or

receive data register

9S12C329S12DP5129S12DP512PS0PS2PS0


SCI Details

SCI1BD: Determines the baud rate: Say SCI1BD[12:0] => Integer BR

SCI Baud-rate = MClock/(16xBR)Mclock on 9S12DP512 is 24 MHz (with PLL in Load

mode); 8 MHz otherwise. TE is the Transmitter Enable bit

RE is the Receiver Enable bit.

Addr Bit 7 6 5 4 3 2 1 Bit 0 Name$00D2 LOOPS SWAI RSRC M WAKE ILT PE PT SCI1CR1$00D3 TIE TCIE RIE ILIE TE RE RWU SBK SCI1CR2$00D4 TDRE RDRF IDLE OR NF FE PF SCI1SR1$00D5 0 0 0 0 BRK13 TXDIR RAF SCI1SR2$00D6 R8 0 0 0 0 0 0 SCI1DRH$00D7 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 SCI1DRL

Addr msb lsb Name$00D0 - - - 12 11 10 9 8 7 6 5 4 3 2 1 0 SCI1BD


… SCI Details

TDRE is the Transmit Data Register Empty flag. set by the SCI

hardware if transmit data register empty

if set, the software can write next output to SCIDRL

cleared by two-step software sequence

o first reading SCISR1 with TDRE set

o then SCIDRL write

RDRF is the Receive Data Register Full flag. set by hardware if a

received character is ready to be read

if set, the software can read next input from SCIDRL

cleared by two-step software sequence

o first reading SCISR1 with RDRF set

o then SCIDRL read


… SCI Details

RIE is the Receive Interrupt Enable bit (Arm). set and cleared by software set to arm RDRF triggered

interrupts clear to disarm RDRF

triggered interrupts TIE is the Transmit Interrupt

Enable bit (Arm). set and cleared by software set to arm TDRE triggered

interrupts clear to disarm TDRE

triggered interrupts

SCI1DRL register contains transmit and receive data these two registers

exist at the same I/O port address

Reads access the read-only receive data register (RDR)

Writes access the write-only transmit data register (TDR)


SCI I/O Programming

; Initalize 9S12DP512 SCI at 38400 bps; Inputs: none ; Outputs: none; Errors: none; assumes 8 MHz E clock (PLL not activated)SCI1_Init movb #$0c,SCI1CR2 ; enable SCI TE=RE=1 movw #13,SCI1BD ; 38400 bps; baud rate(bps)= 8000000/(16xBR) (38461.5) rts


…SCI I/O Programming

InChar

RDRF

ReadSCDR

0

1

rts

***********SCI_InChar**************** Input one character from SCI* Inputs: none* Outputs: RegA is ASCII character* Registers modified: CCRRDRF equ $20SCI_InChar

brclr SCISR1,#RDRF,SCI_InChar* RDRF=1 when a new key is available

ldaa SCIDRL ASCII characterrts

* * * * End of SCI_InChar * * * * * *


…SCI I/O Programming

*********SCI_OutChar****************** Output one character to SCI* Inputs: RegA is ASCII char* Outputs: none* Registers modified: CCRTDRE equ $80SCI_OutChar

brclr SCISR1,#TDRE,SCI_OutChar* TDRE=1 when ready for more output

staa SCIDRL Start Outputrts

* * * ** End of SCI_OutChar * * * * *

OutChar

TDRE

WriteSCDR

0

1

rts

Re-visit Tut3


Overrun Error

If there is already data in the SCI0DRL when the shift register is finished, it will wait until the previous frame is read by the software, before it is transferred. An overrun occurs when there is one receive frame in the SCI0DRL, one receive frame in the receive shift register, and a third frame comes into RxD.

"2"=$32s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s

"3"=$33"1"=$31

$31 SCI0DRLRDRF=1 $32 Shift reg OVRN=1


Tut2

Busy-wait SCI input I/O bound (bandwidth limited to input rate) Very inefficient (spends a lot of time waiting)


Tut2: Recover wasted time?

Technique 1: Combine all busy-waits

Requires cooperation, Complicated to test

(all tasks are interrelated)

Can’t guarantee bound on latency

Device 1

Ready

Input/Output

Data 1

Busy

Other functions

Device 2

Ready

Input/Output

Data 2

Busy

Device n

Ready

Input/Output

Data n

Busy


Tut2: Recover wasted time?

Technique 2: Input device interrupts when ready

ISR reads new input, puts into FIFO Latency equals maximum time it runs with

I=1

Source processProducerFIFOorDouble buffer Sink processConsumer

Put Get

FIFO queues and double buffers can be used to pass data from a producer to a consumer


FIFO Queues

Arm output

Write datato outputDisarmoutput

Full TxFifo

Not emptyEmpty

TxPutFifoNot full

TxGetFifo

rti

TxFifoRead datafrom input

ERROR

Not empty

Empty

InChar

RxGetFifo RxPutFifoNot full

Full

rti

RxFifoRxFifo

rts

Input ISR

OutChar

rts

Output ISR

Figure 12.6: FIFO queues can be used to pass data between threads


Tut4: Producer Consumer problem


FIFO: Two Implementations

Differ in the way empty/full conditions are determined:Two pointers (12.3.3, Tut4):

o Empty => GetPt == PutPt o Full => GetPt ==(PutPt+1)%buffer_sizeo Wastes 1 buffer slot

Two pointers with a countero Empty => counter == 0o Full => counter = buffsizeo Uses all buffer slots


FIFO: Two Implementations

Common to both ImplementationsGetPt: Points to the data that will be

removed on the next call to FiFo_Get PutPt: Points to the empty space where the

data will be stored on the next call to Fifo_Put

Fifo_Put adds data at PutPt and increments PutPt

FiFo_Get removes data at GetPt and decrements GetPt

Wrapping must be handled because buffers are not infinite


Wrap

GPt

Put

PPt

oldestnewest

GPt

PutPPt

oldest

newest

GPt

Put

PPt

oldest

newest

GPt

PPt

oldest

newest

GPt

Put

PPt

Get Get Get

GPt

PPt

oldest

newest

Get

GPt

PPt

oldest

newestPPt

newest

GPt oldest

PPtnewest

GPt oldest

PPtGPt

Pointer wrapon 2nd put

Pointer wrapon 4th get


Lab9

Figure 8.3: Data flows from the sensor through the two microcontrollers to the LCD. The output compare timer is used to trigger the real-time sampling. Use the special serial cable to connect the two SCI1 ports.

1.5 cm

1.50 cm


Lab9

Communication interfacing between two 9S12 microcontrollers using SCI


Simple Design

Courtesy: Jon Valvano


Issues in Lab 9

Synchronizationo Blind-Cycleo Busy Waito Interrupt

FIFOStructured mechanism to pass data.Helps us cope with mismatched speeds of

producer and consumer

Source processProducerFIFOorDouble buffer Sink processConsumer

Put Get


Lab 9 Transmitter

Context SwitchWhen a previously scheduled interrupt (OC

interrupt) occurs, the processor has to switch context to run the corresponding ISR.

What does this entail:o The current instruction (of the foreground process)

is finishedo Push registers (including CCR) on Stack (with I=0)o Disable further interrupts (I=1)o Vector fetch and load ISR address into PC

Demo in TExaS with Transmitter


…Lab 9 Transmitter

When does the OC Interrupt occur? 3 conditions must be true

o Arm the Specific Interrupt: (C0I=1) - ritual o Interrupts enabled: (I=0 using cli) - ritualo Interrupt gets Triggered: C0F is set when TCNT equals

TC0

What happens in ISR? Acknowledge Interrupt:

movb #$01,TFLG1 Read ADC data, encode, send one frame rti

Note: It is not necessary for you to set/clear the I bit except in the initial ritual, it is done automatically


Lab 9 Receiver

Context Switch When a scheduled interrupt (SCI RDRF interrupt) occurs, the

processor has to switch context to run the corresponding ISR.

When does the SCI RDRF Interrupt occur? 3 conditions must be true

o Arm the Specific Interrupt: (RIE=1) - ritualo Interrupts enabled: (I=0 using cli) - ritualo Interrupt gets Triggered: RDRF is set when a new frame

arrives What happens in ISR?

Acknowledge Interrupt: By reading SCI0SR1 and SCI0DRL

Read a frame and pass to foreground through global memory; Schedule

rti


Lab 9: Why FIFO?

May use unstructured globals to pass data Is there data in there? Are you writing new data overtop old data? Are you reading garbage?

FIFOs are structured globals Fifo_Put stores data; Fifo_Get retreives data First in first out means the data remains in order Real way to implement thread synchronization

o The producer needs to stall if FIFO is fullo The consumer needs to stall if FIFO is empty

Lab7 way to implement thread synchronizationo The producer throws data away if FIFO is fullo The consumer waits if FIFO is empty


Lab9: Receiver Main program

1. Initialize Timer, LCD, Fifo_Init, SCI2. Fifo_Get (wait here until data is

available)3. Convert from 8-bit sample to decimal

fixed-point4. Display on LCD5. repeat 2,3,4 over and over


Interrupt Programming

5. Disillusionment

!!??++!!!

executing

3. Love2. Excitement

no compile

errors

1. Distrust

Welcome...

crash!

4. Surprise 6. Frustration

error

oh man!

J Vw

13-1 ee 319k introduction to microcontrollers lecture 13: serial communications interface (sci),...

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