11 how to implement an ethercat slaveethercat.org/2014/spain/download/11_how_to_implement_an...how...

How to implement an EtherCAT Slave Device

EtherCAT Slave Architecture

Implementation Process

Device Definition

- Integrated/ Interface Device

- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary

© EtherCAT Technology GroupOct 2014 2

Agenda

1. EtherCAT Slave Architecture Overview

2. Slave Implementation Process Overview

3. First Steps: Device Definition

4. Hardware Design

5. Software Development

6. Conformance Testing

7. Common Issues –and how to avoid them

8. Summary



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


EtherCAT Slave Architecture Overview

EtherCATMaster

EtherCATConfiguration Tool

*.xml

EtherCAT NetworkInformation File (ENI)

*.xml

EtherCAT SlaveInformation File (ESI)

EtherCAT Slave

EtherCAT SlaveArchitecture

NW Interface

*.xml


EtherCAT Slave


NW Interface

*.xml


EtherCAT Slave


NW Interface



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


EtherCAT Slave Architecture Overview

EtherCATMaster

EtherCATConfiguration Tool

*.xml

EtherCAT NetworkInformation File (ENI)

*.xml*.xml*.xml

EtherCAT SlaveInformation Files (ESI)

EtherCAT Slave

Network Interface / Physical Layer

RJ4

5

Mag

netic

PHY

RJ45

Mag

netic

PHY

Device Application / Application Layer

µC or dig. I/O Interface

Process Data Interface (PDI)

Individual HW/SW

ESC / Data Link Layer

EtherCAT Slave Controller (ESC)

EEPROM(ESC config.

Data)

I2CEtherCAT LEDs

EtherCAT Slave

ESC

µC / I/O



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary

© EtherCAT Technology Group

ETG Membership1)

ETG Vendor ID1)

CTT License1)Development Toolkit

EtherCAT Training + Workshops2)

Lab Wiring with µC

ETG

Sup

port

HW / SW Aspects

NW

Inte

rface

ES

C

EE

PR

OM

µC &

PD

I

Com

mun

icat

ion

Pro

toco

ls

Dev

ice

Pro

files

Syn

chro

niza

tion

EtherCAT Feature Configuration / Device Definition

n

Software Development

s

Hardware Development

Device Requirements

Oct 2014 5

Slave Implementation Process

ETG.2200 Implementation Guide1) mandatory step

for selling EtherCAT Devices2) optional, but recommended



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


First: Device Definition

Define / Select:1. Fully integrated Design or

Interfacing Device

2. Hardware Selection1. NW Interface Hardware

2. ESC, EEPROM

3. µC, PDI

3. Device Profile

4. Parameter + Process Data

5. Synchronization and Time Stamping Requirements



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Fully Integrated or Interfacing Device?

Oct 2014 7

Fully integrated

PRO:

Lower hardware costs

Most flexible solution

Full control of all features

CONTRA:

Higher development costs

Interfacing device

PRO:

Lower development costs

Time to market

Less network know-howrequired

CONTRA:

Higher hardware costs

Form factor restrictions



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Fully integrated Design*:

Application Layer

Data Link Layer

Physical Layer

EtherCAT Slave

Network Interface

RJ4

5

Mag

netic

PHY

RJ45

Mag

netic

PHY

Device Application



ESC


EEPROM(ESC config.

Data)

I2CEtherCAT LEDs

Oct 2014

Hardware Selection

* Interfacing Device Hardware Selection: No generic rulesdue to the diverse architectures of the various solutions

8



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary

© EtherCAT Technology GroupOct 2014

Hardware Selection

• Simple (digital I/O) Devices do not require a µC

• Tasks of Host µC in more complex devices:– Process data – Exchange with the Application– Object Dictionary Handling– Handling of Application Parameter

(Communication Parameter are handled by ESC)– TCP/IP Stack Handling – if required

• Host Controller Performance is determined by Device Application, not by EtherCAT In many cases an 8bit µC is sufficient

9



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


The host controller may determinethe interface to internal DPRAMof the EtherCAT Slave Controller

Example: Beckhoff ASICs:• 8/16 Bit µC Interface

– Demultiplexed– Intel Signal Types– Polarity configurable (BUSY, INT)– Typical µC: ARM, Infineon 80C16x, Hitachi SH1, ST10, TI

TMS320 Series, …

• Serial – Interface (SPI)– Up to 10 MBaud– µC is SPI Master– Typical µC: Microchip PIC, DSPic, Intel 80C51, Atmel AVR…

EtherCAT Slave

µC User Application Software

RJ4

5 RJ45

Mag

netic

PHY

Mag

netic

PHY

Process Data Service Data Processes

ESC Process Data Interface

Mailbox Data Process Data ESC & EtherCAT Configuration

Application Mapping

Dual Port Memory

FMMU, Sync Manager Registers

Oct 2014

EtherCAT Host Controller Interface?

10



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


• Number (and type) of ports• Typical: 2-port devices, for line and ring topologies• 3+4-port devices cater for topology options

4 Ports

Oct 2014

Selection Criteria EtherCAT Slave Controller

11

2 Ports 3 Ports

3 Ports 2 Ports2 Ports

2 Ports2 Ports

2 Ports

2 Ports



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


• Size of DPRAM and no. of Sync Manager entities (SM)

EtherCAT Slave Controller

Oct 2014


DPRAM

SM 3

SM 2

SM 1

SM 0Mailbox Out

Mailbox InParameter Data(acyclic)

Process Data(cyclic)

Buffer 1

Buffer 2

Buffer 3

Buffer 1

Buffer 2

Buffer 3

0x0

4KByte0x0FFF

0x1000

1..60KByte

0xFFFF

12

Data Link LayerConfiguration Registers

Output Data

Input Data



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


• Size of DPRAM and no. of Sync Manager entities (SM)

EtherCAT Slave Controller

Oct 2014


DPRAM

SM 3

SM 2

SM 1

SM 0Mailbox Out

Mailbox InParameter Data(acyclic)

Process Data(cyclic)

Buffer 1

Buffer 2

Buffer 3

Buffer 1

Buffer 2

Buffer 3

0x0

4KByte0x0FFF

0x1000

1..60KByte

0xFFFF

13

Data Link LayerConfiguration Registers

Output Data

Input Data Input Data

Input Data

Output Data

Output Data

Output Data

Input Data

Input Data



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary



• No. of Fieldbus Memory Management Units (FMMU)• FMMUs copy process data from EtherCAT datagrams

to DPRAM – and ensure data consistency• Mechanism for further optimization of resources

(bandwidth, CPU power)

14

EtherCAT Slave 3

ESC (DPRAM)

Dig. I/O

FMMU1 (Outputs)Address: AdrLogical+OffsetD1Length: OUT3Length

FMMU2 (Inputs)Address: AdrLogical+OffsetD1Length: IN3Length

FCSEthernet HDR

ECATHDR Command AdrLogical Length

EtherCATMaster

ECAT Slave 2µC

ESC

ECAT Slave 4µC

ESC

EtherCAT Data

OffsetD1

IN1OUT1 OUT3

ECAT Slave 1Dig. I/O

ESC

Process Data in Shared DatagramShared Command

IN3



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary



• No. of Fieldbus Memory Management Units (FMMU)• FMMUs copy process data from EtherCAT datagrams

to DPRAM – and ensure data consistency• Mechanism for further optimization of resources

(bandwidth, CPU power)• Typical requirement: minimum of 3.

FMMU Number Usage1 Output Data2 Input Data3 Status check of Mailbox Response

15



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary



• Price?• Local Support?• Housing?• Size?• Integrated PHYs?

– Hilscher netX, Renesas R-IN• Integrated CPU?

– TI Sitara™, Hilscher netX, Renesas R-IN– FPGA solutions (optional: softcore)

• Multi Protocol Support– Hilscher netX– FPGA solutions– TI Sitara™ – Renesas R-IN

• Dedicated for EtherCAT– Beckhoff ET1100, ET1200

16



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


EtherCAT Slave Controller Timeline

Oct 2014

ESC10/20:Altera® Cyclone™-I

IP-Core forAltera®

Cyclone™-II

Beckhoff ®

ET1100

Beckhoff ®

ET1200Hilscher

netX® 100/500

HilschernetX® 50

IP-CoreXilinx®

Spartan™-3

IP-Core forAltera®

Cyclone™-III

IP-Core forXilinx®

Spartan™-6IP-Core for

Altera®

Stratix™-IV

IP-Core forAltera®

Cyclone™-IV

IP-Core for Xilinx® Kintex™-7

IP-Core for Altera® Stratix™-V

IP-Core for FPGA ofIntel® Atom™ E6x5C

TI's Sitara™

µP family

HilschernetX® 51/52/6

IP-Core forXilinx®

Artix™-7 + Zync™

RenesasR-IN32M3-EC

AnybusNP40

InnovasicFido5000

IP-Core forAltera® Cyclone™-V

March 2014 17



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Physical Layer, Network Interface?

EtherCAT Physical Layer is 100BASE-TX or –FX*

EtherCAT PHYs have to support• Full Duplex Communication• Auto-Negotiation, MDI/MDI-X auto-crossover• MII with MII management interface• PHY link loss reaction time (link loss to link

signal/LED output change) shorter than 15µs (for short redundancy switchover)

For further details see the ESC Datasheets or the corresponding PHY Selection Guide

* + LVDS for modular devices, supported by Beckhoff ASICs only18



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Device Profile?

• Which device profile shall be supported?• Drives: The CiA402 (CANopen) & Sercos Profiles are

mapped to EtherCAT

• If the device can be described as hardware modules or aslogical modules:– Modular Device Description recommended– Modular Device Profile (ETG.5001)

19

IEC 61800-7-300Mapping of Profiles toNetwork Technologies

IEC 61800-7-300Mapping of Profiles toNetwork Technologies

IEC 61800-7-200Profile SpecificationsIEC 61800-7-200Profile Specifications

IEC 61800-7-1Interface DefinitionIEC 61800-7-1Interface Definition

IEC SpecificationIEC Specification IEC 61800-7 – Generic Interface and Use of Profiles for Power Drive Systems

Annex AMapping to CiA402

IEC 61800-7-201Profile CiA402

IEC 61800-7-301

CANopen** EPL EtherCAT

Annex BMapping to CIP

IEC 61800-7-202Profile CIP Motion

IEC 61800-7-302

Annex CMapping to PROFIdrive

IEC 61800-7-203Profile PROFIdrive

IEC 61800-7-303

Annex DMapping to SERCOS*

IEC 61800-7-304Profile SERCOS

IEC 61800-7-304

SERCOS I/II SERCOS III EtherCAT



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Parameter + Process Data?

Device Profile determines Parameters and Process Data setupBut: Decision if the Process Data Layout shall be:→ Fixed: cannot be changed by user.

Example: simple I/O device.

→ Selectable: user can select between several predefined process data layouts.Example: drive where process data layout depends on the selected drive operation mode

→ Determined by module combination (Dynamic): determined at device bootup by actual hardware modules; Example: bus coupler with modular I/O.

20



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Synchronization and Time Stamping?

What level of Synchronization is required?1. Freerun:

local timer controls application, no synchronization with network

2. Synchronized with network cycle: local application triggered by reception of process data (“SM-event”). Jitter mainly depends on master accuracy.

3. Synchronized by Distributed Clocks: local application triggered by high precision and fully synchronized hardware interrupt generated by local clock; accuracy in the order of nanoseconds

21



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Lab Wiring with µC

HW/SW Integration

ETG

Sup

port

HW / SW Aspects

Debugging withWireshark + CTT

Loca

l A

pplic

atio

n

ES

I


Official EtherCAT Conformance Test

In-house Conformance Test with CTT1)

according to ETG.7000.2 Conformance Test Record

Integration

Phy

sics

Ele

ctro

nics


Integrated Interoperability Tests, Plug Fests, Network System Tests, Pilot Applications

Product Release

Oct 2014 22

Hardware Design

ETG.2200 Implementation Guide

1) mandatory step for selling EtherCAT Devices



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


EtherCAT Slave

Bus Interface / Physical Layer

RJ4

5

Mag

netic

PHY

RJ45

Mag

netic

PHY




Individual HW/SW

ESC / Data Link Layer


EEPROM(ESC config.

Data)

I2CEtherCAT LEDs

Oct 2014

Hardware Design

23

Application / Host ControllerAccording to Application Requirements

EtherCAT Slave ControllerAccording to ESC Selection Criteria

Network Interface / Physical LayerStandard Ethernet Interface, Requirementsaccording to PHY Selection Guide / ESC Datasheet



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Lab Wiring with µC

HW/SW Integration

ETG

Sup

port

HW / SW Aspects


Loca

l A

pplic

atio

n

ES

I





Integration

Phy

sics

Ele

ctro

nics



Product Release

Oct 2014 24






Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Device Description: ESI File

• Each EtherCAT Slave device is described by an„EtherCAT Slave Information“ (ESI) File in XML Format

• The ESI Format is definedin the ETG.2000 spec

• Of course there are also schemas, example files etc.on the EtherCAT website

• The ESI alsosupports thedescription ofmodular devices

25

*.xml*.xml*.xml

EtherCAT SlaveInformation Files (ESI)



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary



Typical Software-Structure:• Applications-Program/Firmware• Communication-Stack with following elements:

– EtherCAT State Machine– Verification of configuration settings– Handling of synchronization + configuration errors

– Mailbox-Protocol Handling– Most common protocol: CoE– Error Handling (e.g. Parameter cannot be read or written)

– Access to ESC memory (DPRAM)– Synchronization

The listed functionality is supported by most available stacks, such as

– Beckhoff Slave Stack Code (free of charge for ETG members)– Hilscher EtherCAT Slave Stack

26



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary



Example: Structure of Beckhoffs Slave Stack Code

27

EtherCAT Slave


ESC / DataLink Layer

µCUser Application Software

ESC

PDI

Slave Sample Code

ESC Memory Interface

Mailbox

CoE

SoE

EoE FoE

AoE Process Data

HandlerEtherCAT

State Machine

Local Communication Application

Network Interface / Physical Layer

RJ4

5 RJ45



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Conformance: Plug Fests

• Plug Fests are Developer Interoperability Meetings• Most helpful and well attended:

2/y in Europe, 1-2/y in Asia, 1/y in North America

28



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Lab Wiring with µC

HW/SW Integration

ETG

Sup

port

HW / SW Aspects


Loca

l A

pplic

atio

n

ES

I





Integration

Phy

sics

Ele

ctro

nics



Product Release

Oct 2014 29

Conformance Testing





Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Conformance Testing

• The EtherCAT Conformance Test Tool (CTT) is helpful throughout the implementation – and afterwards

• Having the CTT and testing with it is a requirement• Recommended Procedure (see Conformance Guide):

– If not yet ETG member: Join ETG (free of charge)– Obtain EtherCAT Vendor ID (free of charge)– Subscribe to Conformance Test Tool– Conformance Test Record (ETG.7000-2) is Test Guideline

• Test with CTT• Test of the LED behavior (ETG.1300)• Marking and Trademark Hints (ETG.9001)• Further tests

• Test at official EtherCAT Test Center (and Certification) is optional, but highly recommended

30



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Common Issues – and how to avoid them!

The 5 „Killers“ for passing the conformance test:

1. Logo:Neither on the device nor in thedocumentation the EtherCAT logo is shown

2. Trademark: Trademark hint is missing in the documentation

3. Indicator and Port Marking:Marking is missing or misleading

4. Watchdog Behavior:If sending of process data is stopped the devicedoes not show the required behavior

5. DC-Signal Monitoring:If the interrupt for the synchronization is disabledthe device does not show the required behavior

31

©

IN/OUT?



Device Definition


- HardwareSelection

- Device Profile

- Process Data

- Synchronization

HW Design

SW Development

Conformance

Common Issues

Summary


Summary

1. Implementing EtherCAT is relatively simple: the demanding parts are embedded in the EtherCAT Slave Controller chip

2. ETG (and its members) provide all the information andsupport for the implementation of EtherCAT

3. Tools, Stacks, Support Documents, Implementation Guidelines, Developers Forum etc. are all in place- and well proven.

4. EtherCAT is a stable technology, that has beensuccessfully implemented by a large number of vendors

5. See also: EtherCAT Slave Implementation Guidelinewww.ethercat.org/ETG2200

32