1

Finite State Machines (FSMs)

Now that we understand sequential circuits, we can use them to build:

Synchronous (Clocked) Finite State Machines

Finite number of states

Flip-flops/latches run on clock signal(s)

2

• FSM components:– Next state logic (combinational): next state = f(current state, inputs)– Memory (sequential): stores state in terms of state variables– Output logic (combinational): function depends on FSM type:

• Moore Machine: output = g(current state)

• Mealy Machine: output= g(current state, inputs)

Next-State Logic

Output LogicState

(memory)

Inputs

Outputs

Clock

Next-State Logic

Output LogicState

(memory)

Inputs

Outputs

Clock

3

FSM Analysis

• Goal: Given a FSM circuit, describe the circuit’s behavior

D Q

QB

D Q

QB

Mux

1

0

CLK

D0

D1

EN

QTR

Q0

Q1

4

• Excitation equations describe memory (FF or latch) input signals as a function of inputs and current state (i.e., state variables)

00 QEND

1101 QENQQEND

Excitation Equations:

D Q

QB

D Q

QB

Mux

1

0

CLK

D0

D1

EN

QTR

Q0

Q1

5

• Transition equations describe the next state as a function of inputs and current state– Generated by substituting the excitation equations into the

characteristic equation for the sequential gates

000 QENDQ

11011 QENQQENDQ

Transition Equations:

DQ

D FF Characteristic Eqn:

This step is trivial when using D FFs!

D Q

QB

D Q

QB

Mux

1

0

CLK

D0

D1

EN

QTR

Q0

Q1

6

• Output equations describe the output signals as a function of the current state (for a Moore machine) or as a function of the current state and inputs (for a Mealy machine)

10 QQQTR

Output Equation:

D Q

QB

D Q

QB

Mux

1

0

CLK

D0

D1

EN

QTR

Q0

Q1

7

current state

inputoutput

next state

• The transition/output table shows the next state and output for every current state/input combination– Entries of the table are obtained from the transition equations

and the output equations

000 QENDQ

11011 QENQQENDQ

Transition Equations:

10 QQQTR

Output Equation:

Q1 Q0

EN0 1 QTR

0 00 11 01 1

Q1 Q0+ +

00 0101 10

00

10 1111 00

01

Transition/Output Table:D Q

QB

D Q

QB

Mux

1

0

CLK

D0

D1

EN

QTR

Q0

Q1

8

• State labels are a one-to-one mapping from state encodings to state names

• The state/output table has the same format as the transition table, but state names are substituted in for state encodings

Q1 Q0

0 00 11 01 1

BCD

State name

A

00 0101 10

00

10 1111 00

01

Q1 Q0

EN0 1 QTR

0 00 11 01 1

Q1 Q0+ +

Transition/Output Table: State/Output Table:

A BB C

00

C DD A

01

SEN

0 1 QTRABCD

S+

Q1 Q0

0 00 11 01 1

BCD

State name

A

State Assignments

9

• A state diagram is a graphical representation of the information in the state/output table

• Nodes (or vertices) represent states– Moore machines: output

values are written in state node

• Arcs (or edges) represent state transitions– Labeled with a transition

expression• when an arc’s transition

expression evaluates to 1 for a given input combination, that arc is followed to the next state

– Mealy machines: output values (or expressions) are written on arcs

EN

EN

EN

EN

EN EN

ENEN

State/Output Table:

A BB C

00

C DD A

01

SEN

0 1 QTRABCD

S+

State Diagram:

AQTR = 0

DQTR = 1

BQTR = 0

CQTR = 0

10

FSM Analysis Recap

1) Find the circuit’s excitation equations2) Using the excitation and characteristic equations, write

the circuit’s transition equations3) Write the circuit’s output equations4) From the transition and output equations, create the

circuit’s transition/output table5) Create state labels6) Using the transition table and state labels, create the

state table7) (optional) Draw the circuit’s state diagram

11

FSM Design

• Goal: Design a FSM that satisfies the requirements of the given problem description (spec.)

• Follow FSM analysis steps in reverse! (more or less)

1) (optional) Construct state diagram2) Construct state/output table3) Create state assignments4) Create transition/output table5) Choose FF type6) Construct excitation/output table

- Similar to transition/output table

7) Find excitation and output logic equations

“Art of design”

“Turn the crank”

12

SIN

0 1 OUTzero1sone1two1s

three1s

S+

FSM Design Example

• Problem description: design a Moore FSM with one input IN and one output OUT, such that OUT is one iff IN is 1 for three consecutive clock cycles

• State table:

zero1s one1two1sthree1s

zero1szero1szero1s three1s

0001

13

• State Assignments– How many state variables are needed to encode

four states?

– In general, if we have n states, how many state variables are needed to encode those states?

n2log

Q1 Q0

0 00 11 01 1

one1two1s

three1s

Statename

zero1s

2

These state assignments may seem rather arbitrary – that’s because they are! We will soon see the impact that state assignments have on our final circuit…

14

• Transition/output table

• Choose FF type: – Using D flip-flops will simplify things (as we’ll see below…)

• Excitation table– Shows FF input values required to create next state values for every current

state/input combination– If we’re designing with D FFs, entries in excitation/output table are the same as

those in transition/output table! • Because of D FF characteristic equation: Q+ = D

0001

SIN

0 1 OUTzero1sone1two1s

three1s

S+

zero1szero1szero1szero1s

one1two1s

three1sthree1s

00 0100 10

00

00 1100 11

01

Q1 Q0

IN0 1 OUT

0 00 11 01 1

Q1 Q0+ +

State/Output Table: Transition/Output Table:

00 0100 10

00

00 1100 11

01

Q1 Q0

IN0 1 OUT

0 00 11 01 1

D1 D0

Q1 Q0

0 00 11 01 1

one1two1s

three1s

Statename

zero1s

State Assignments

15

• Excitation Logic

00 0100 10

00

00 1100 11

01

Q1 Q0

IN0 1 OUT

0 00 11 01 1

D1 D0

1 1 1

00 01 11 10

0

1

Q1Q0IN

D1

1 1 1

00 01 11 10

0

1

Q1Q0IN

D0

• Output Logic

10

101

QQIN

INQINQD

01

010

QQIN

INQINQD

01 QQOUT

Excitation/Output Table:

16

• Circuit:

101 QQIND

010 QQIND 01 QQOUT

Excitation Equations: Output Equation:

D Q

QB

D Q

QB

CLK

D0

D1

IN

OUT

Q0

Q1

17

In Class Exercise

• Design a state/output table for the following problem specification:

Combination lock: Two inputs, X and Y, encode a binary number between 0 and 3 (X is MSB, i.e., XY = 10 →2). A single output signal UNLOCK should be set to 1 iff the sequence 1, 2, 1 occurs on the inputs in three consecutive clock cycles

0001

X Y00 UNLOCK

ABCD

AAAA

BBDB

01ACAC

10AAAA

11S

S+

got nothinggot “1”

got “1,2”got “1,2,1”

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FSM Transition List Design:50’s Vending Machine

• Inputs– d: asserted when user inserts dime– n: asserted when user inserts nickel– c: asserted when user presses candy button– s: asserted when user presses soda button

• Outputs– dc: dispenses candy when asserted– ds: dispenses soda when asserted– cr: 4-bit unsigned number, represents the user’s credit

• Specifications– All inputs are one-hot– Candy costs 10 cents, soda costs 15 cents– Money need only be counted up to 15 cents

19

Vending Machine State Diagram and Transition List

Acr = “0”dc = 0ds = 0d

n

dn

d+n

s

c

c

1

11

s∙c

n∙d

n∙c

n∙d

Bcr = “5”dc = 0ds = 0

Ccr = “10”dc = 0ds = 0

Ecr = “15”dc = 0ds = 0

Fcr = “5”dc = 1ds = 0

Gcr = “0”dc = 0ds = 1

Dcr = “0”dc = 1ds = 0

A 0 0 0

B 0 0 1

C 0 1 0

D 0 1 1E 1 0 0

F 1 0 1G 1 1 0

Q2Q1Q0

TransitionExpression

nd

n∙d

0 0 1Q2Q1Q0

+ + +S S

+

B0 1 0C0 0 0A

nd

n∙d

CEB

0 1 01 0 00 0 1

A 0 0 0A 0 0 0

B 0 0 1B 0 0 1

n+dc

n∙d∙c

EDC

1 0 00 1 10 1 0

C 0 1 0C 0 1 0

1 A 0 0 0cs

s∙c

FGE

1 0 11 1 01 0 0

E 1 0 0E 1 0 0

11

B 0 0 1A 0 0 0

Transition List

cr dc ds“0” 0 0A 0 0 0“5” 0 0B 0 0 1“10” 0 0C 0 1 0“0” 1 0D 0 1 1“15” 0 0E 1 0 0“5” 1 0F 1 0 1“0” 0 1G 1 1 0

Q2Q1Q0

Output Table

20

A 0 0 0

B 0 0 1

C 0 1 0

D 0 1 1E 1 0 0

F 1 0 1G 1 1 0

Q2Q1Q0

TransitionExpression

nd

n∙d

0 0 1Q2Q1Q0

+ + +S S

+

B0 1 0C0 0 0A

nd

n∙d

CEB

0 1 01 0 00 0 1

A 0 0 0A 0 0 0

B 0 0 1B 0 0 1

n+dc

n∙d∙c

EDC

1 0 00 1 10 1 0

C 0 1 0C 0 1 0

1 A 0 0 0cs

s∙c

FGE

1 0 11 1 01 0 0

E 1 0 0E 1 0 0

11

B 0 0 1A 0 0 0

Transition List

cr dc ds“0” 0 0A 0 0 0“5” 0 0B 0 0 1“10” 0 0C 0 1 0“0” 1 0D 0 1 1“15” 0 0E 1 0 0“5” 1 0F 1 0 1“0” 0 1G 1 1 0

Q2Q1Q0

Output Table

22 QD

012012

01201201200

QQQcQQQ

cQQQdnQQQnQQQQD

sQQQcdnQQQ

cQQQnQQQdQQQQD

012012

01201201211

012012 QQQQQQdc

012 QQQds

…

dQQQ 012 )(012 dnQQQ

csQQQsQQQcQQQ 012012012

21

50’s Vending Machine: Mealy Implementation

c, dc = 1

c, dc = 1

s, ds = 1

Acr = “0”

dn

dn

d+n

s∙c

n∙d

n∙c

n∙d

Bcr = “5”

Ccr = “10”

Ecr = “15”

Outputs are assumed to be 0 unless stated otherwise

The Mealy implementation uses fewer states, and therefore fewer FFs!

22

0 1 0 1

0 1 0 0

00 01 11 10XY

Q1Q0

0 1 0 1

0 0 0 0

00

01

11

10

Q0+

0 0 0 1

0 0 0 0

00 01 11 10XY

Q1Q0

0 0 0 1

0 1 0 0

00

01

11

10

Q1+

State Assignments• Back to our combinational lock example…

SABCD

Q1 Q0

0 00 11 11 0

Minimal SOP: 26 literals

Perhaps we can do better using smarter state assignments…

0001

X Y00 UNLOCK

0 00 11 11 0

00000000

01011001

0100110011

1000000000

11

Q1 Q0+ +

Q1Q0

0001

X Y00 UNLOCK

ABCD

AAAA

BBDB

01ACAC

10AAAA

11S

S+

Minimal POS: 20 literals

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• Another state assignment approach– Maximize the number of 1’s

SABCD

Q1 Q0

1 10 11 00 0

0001

X Y00 UNLOCK

ABCD

AAAA

BBDB

01ACAC

10AAAA

11S

S+

0001

X Y00 UNLOCK

1 10 11 00 0

11111111

01010001

0111101110

1011111111

11

Q1 Q0+ +

Q1Q0

Using smarter state assignments improved the next-state circuit cost from 20 literals to 9 literals!

1 0 1 1

1 0 1 1

00 01 11 10XY

1 0 1 1

1 0 1 1

00

01

11

10

Q0+

1 1 1 0

1 1 1 0

00 01 11 10XY

Q1Q0

1 0 1 1

1 1 1 1

00

01

11

10

Q1+

Q1Q0

Minimal SOP: 10 literals

Minimal POS: 9 literals

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• Another approach: use more flip-flops– one-hot encodings (with the addition of 000)

0112

0112

0120120120

QQYXQQYX

QQQQYX

QQQQQQQQQYXQ

0120121 QQQYXQQQYXQ

0122 QQQYXQ

SABCD

Q2 Q1

0 00 00 11 0

Q0

0100

0001

X Y00 UNLOCK

0 0 00 0 10 1 01 0 0

000000000000

01 10 11Q1Q0Q2

001001100001

000010000010

000000000000

Q1 Q0+ +Q2

+

0001

X Y00 UNLOCK

ABCD

AAAA

BBDB

01ACAC

10AAAA

11S

S+

Read minterms directly off of transition table:

23 literals

How many states are really in our new state machine?

What happened to the other 4 states???

25

Unused States• Previous design: all

unused states were implicitly assigned a next state of 000 (state A)

• This is known as a safe design– If noise causes the

machine to enter an unused state, it will return to a used state under any input conditions

0001

X Y00 UNLOCK

0 0 00 0 10 1 01 0 0

000000000000

01 10 11Q1Q0Q2

001001100001

000010000010

000000000000

Q1 Q0+ +Q2

+

0 1 11 0 11 1 01 1 1

000000000000

000000000000

000000000000

000000000000

0000

u1u2u3u4

A B

C D

u1 u2

u3 u4

Current State

A B

C D

u1 u2

u3 u4

Next State

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• Efficient Design: Treat the next-states and outputs of unused states as don’t cares– Minimizes circuit cost!

• If an unused state is ever entered, state machine may never return to normal operation

0001

X Y00 UNLOCK

0 0 00 0 10 1 01 0 0

000000000000

01 10 11Q1Q0Q2

001001100001

000010000010

000000000000

Q1 Q0+ +Q2

+

0 1 11 0 11 1 01 1 1

dddddddddddd

dddddddddddd

dddddddddddd

dddddddddddd

dddd

u1u2u3u4

A B

C D

u1 u2

u3 u4

Current State

A B

C D

u1 u2

u3 u4

Next State

Finding transition equations now requires 5-variable K-maps!

27

• State clustering assigns unused states to behave like used states

• If noise causes an unused state to be entered, the machine will return to a used state in a single clock cycle

0001

X Y00 UNLOCK

0 0 00 0 10 1 x1 x x

000000000000

01 10 11Q1Q0Q2

001001100001

000010000010

000000000000

Q1 Q0+ +Q2

+

Represents 010 (C) and 011 (u1)

Represents 100 (D), 101 (u2), 110 (u3), and 111 (u4)

A B

C D

u1 u2

u3 u4

Current State

A B

C D

u1 u2

u3 u4

Next State