02_computer evolution and performance [compatibility mode]

8/11/2019 02_Computer Evolution and Performance [Compatibility Mode]

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ENIAC !ac"ground

Electronic Numerical Integrator AndComputer

Eckert and Mauchly University of Pennsylvania

Tra ector ta!les for "ea ons

#tarted $%&'

(inished $%&)

*Too late for "ar effort Used until $%++


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ENIAC details

,ecimal -not !inary.

/0 accumulators of $0 digits

Programmed manually !y s"itches $12000 vacuum tu!es

$+2000 s3uare feet

$&0 k4 po"er consumption

+2000 additions per second


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von Neumann#$uring

#tored Program concept

Main memory storing programs and data

A5U operating on !inary data Control unit interpreting instructions from

memor and e6ecutin

Input and output e3uipment operated !ycontrol unit

Princeton Institute for Advanced #tudies

*IA#

Completed $%+/


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IAS details

$000 6 &0 !it "ords*7inary num!er

*/ 6 /0 !it instructions #et of registers -storage in CPU.

*Memory 7uffer 8egister

* ry r r*Instruction 8egister

*Instruction 7uffer 8egister

*Program Counter

*Accumulator

*Multiplier 9uotient


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Structure of IAS %

detail


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I&'

Punched;card processing e3uipment

$%+' ; the :0$

*I7M=s first stored program computer*#cientific calculations

$%++ ; the :0/

*7usiness applications

5ead to :00>:000 series


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$ransistors

8eplaced vacuum tu!es

#maller

Cheaper 5ess heat dissipation

Made from #ilicon -#and.

Invented $%&: at 7ell 5a!s

4illiam #hockley et al?


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$ransistor &ased Computers

#econd generation machines

NC8 @ 8CA produced small transistor

machines I7M :000

,EC ; $%+:

*Produced P,P;$


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'oore)s *a+

Increased density of components on chip

ordon Moore co;founder of Intel

Num!er of transistors on a chip "ill dou!le everyyear

#ince $%:0=s development has slo"ed a little

*

Cost of a chip has remained almost unchanged

Figher packing density means shorter electricalpaths2 giving higher performance

#maller siGe gives increased fle6i!ility 8educed po"er and cooling re3uirements

(e"er interconnections increases relia!ility


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I&' -./ series

$%)&

8eplaced -@ not compati!le "ith. :000

series (irst planned familyB of computers

*#imilar or identical instruction sets

*#imilar or identical D>#*Increasing speed

*Increasing num!er of I>D ports -i?e? more

terminals.*Increased memory siGe

*Increased cost

Multiple6ed s"itch structure


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0EC P0P8

$%)&

(irst minicomputer -after miniskirtH.

,id not need air conditioned room #mall enough to sit on a la! !ench

2

*$00kJ for I7M ')0

Em!edded applications @ DEM

7U# #T8UCTU8E


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Semiconductor 'emor1

$%:0

(airchild

#iGe of a single core*i?e? $ !it of magnetic core storage

Non;destructive read

Much faster than core

Capacity appro6imately dou!les each year


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Intel

$%:$ ; &00&

*(irst microprocessor

*All CPU components on a single chip*& !it

(ollo"ed in $%:/ !y 1001

*1 !it*7oth designed for specific applications

$%:& ; 1010

*Intel=s first general purpose microprocessor


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Speeding it up

Pipelining

Dn !oard cache

Dn !oard 5$ @ 5/ cache 7ranch prediction

#peculative e6ecution


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Performance &alance

Processor speed increased

Memory capacity increased

Memory speed lags !ehind processorspeed


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*ogin and 'emor1 Performance (ap


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Solutions

Increase num!er of !its retrieved at onetime

*Make ,8AM "iderB rather than deeperB Change ,8AM interface

*Cache

8educe fre3uency of memory access*More comple6 cache and cache on chip

Increase interconnection !and"idth

*Figh speed !uses*Fierarchy of !uses


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I#O 0evices

Peripherals "ith intensive I>D demands

5arge data throughput demands

Processors can handle this Pro!lem moving data

*Caching

*7uffering

*Figher;speed interconnection !uses

*More ela!orate !us structures

*Multiple;processor configurations


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$1pical I#O 0evice 0ata ates


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3e1 is &alance

Processor components

Main memory

I>D devices Interconnection structures


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Improvements in Chip Organization and

Architecture

Increase hard"are speed of processor

*(undamentally due to shrinking logic gate siGe

More gates2 packed more tightly2 increasing clockrate

Propagation time for signals reduced

*,edicating part of processor chip Cache access times drop significantly

Change processor organiGation and

architecture*Increase effective speed of e6ecution

*Parallelism

C S


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Pro!lems +ith Cloc" Speed and *ogin

0ensit1

Po"er

*Po"er density increases "ith density of logic and clockspeed

*,issipating heat 8C delay

*#peed at "hich electrons flo" limited !y resistance andcapac ance o me a " res connec ng em

*,elay increases as 8C product increases

*4ire interconnects thinner2 increasing resistance

*4ires closer together2 increasing capacitance

Memory latency*Memory speeds lag processor speeds

#olutionK

*More emphasis on organiGational and architecturalapproaches


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Intel 'icroprocessor Performance


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Increased Cache Capacit1

Typically t"o or three levels of cache!et"een processor and main memory

Chip density increased*More cache memory on chip

(aster cache access

Pentium chip devoted a!out $0L of chiparea to cache

Pentium & devotes a!out +0L


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'ore Comple4 E4ecution *ogic

Ena!le parallel e6ecution of instructions

Pipeline "orks like assem!ly line

*,ifferent stages of e6ecution of differentinstructions at same time along pipeline

#uperscalar allo"s multiple pipelines

"ithin single processor*Instructions that do not depend on one

another can !e e6ecuted in parallel


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0iminishing eturns

Internal organiGation of processorscomple6

*Can get a great deal of parallelism

*(urther significant increases likely to !erelatively modest

ene s rom cac e are reac ng m

Increasing clock rate runs into po"erdissipation pro!lem

*#ome fundamental physical limits are !eingreached


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Ne+ Approach % 'ultiple Cores

Multiple processors on single chip

*5arge shared cache

4ithin a processor2 increase in performance

proportional to s3uare root of increase incomple6ity

If soft"are can use multi le rocessors dou!lin

num!er of processors almost dou!lesperformance

#o2 use t"o simpler processors on the chiprather than one more comple6 processor

4ith t"o processors2 larger caches are ustified

*Po"er consumption of memory logic less thanprocessing logic


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48. Evolution 567

1010

* first general purpose microprocessor

* 1 !it data path

* Used in first personal computer Altair

101) +MFG /%2000 transistors* much more po"erful

* $) !it

* instruction cache refetch fe" instructions

* 1011 -1 !it e6ternal !us. used in first I7M PC 10/1)

* $) M!yte memory addressa!le

* up from $M!

10'1)

* '/ !it

* #upport for multitasking

10&1)

* sophisticated po"erful cache and instruction pipelining

* !uilt in maths co;processor


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48. Evolution 527

Pentium

* #uperscalar

* Multiple instructions e6ecuted in parallel

Pentium Pro* Increased superscalar organiGation

* Aggressive register renaming

* !ranch prediction

* data flo" analysis* speculative e6ecution

Pentium II

* MM technology

* graphics2 video @ audio processing Pentium III

* Additional floating point instructions for ', graphics


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48. Evolution 5-7

Pentium &

* Note Ara!ic rather than 8oman numerals

* (urther floating point and multimedia enhancements

Core* (irst 61) "ith dual core

Core /

* )& !it architecture

Core / 9uad 'FG 1/0 million transistors* (our processors on chip

61) architecture dominant outside em!edded systems

DrganiGation and technology changed dramatically Instruction set architecture evolved "ith !ack"ards compati!ility

$ instruction per month added

+00 instructions availa!le

#ee Intel "e! pages for detailed information on processors

Em!edded S stems


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Em!edded S1stems

A'

A8M evolved from 8I#C design

Used mainly in em!edded systems

*Used "ithin product*Not general purpose computer

*,edicated function

*E?g? Anti;lock !rakes in car


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Em!edded S1stems euirements

,ifferent siGes

*,ifferent constraints2 optimiGation2 reuse

,ifferent re3uirements*#afety2 relia!ility2 real;time2 fle6i!ility2

legislation

*5ifespan

*Environmental conditions

*#tatic v dynamic loads

*#lo" to fast speeds

*Computation v I>D intensive

*,escrete event v continuous dynamics


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Possi!le Organization of an Em!edded S1stem


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A' Evolution

,esigned !y A8M Inc?2 Cam!ridge2England

5icensed to manufacturers Figh speed2 small die2 lo" po"er

consumption

P,As2 hand held games2 phones*E?g? iPod2 iPhone

Acorn produced A8M$ @ A8M/ in $%1+

and A8M' in $%1% Acorn2


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A' S1stems Categories

Em!edded real time

Application platform

*5inu62 Palm D#2 #ym!ian D#2 4indo"s mo!ile #ecure applications

Performance Assessment


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Performance Assessment

Cloc" Speed

Oey parameters*Performance2 cost2 siGe2 security2 relia!ility2 po"er

consumption

#ystem clock speed*In FG or multiples of*Clock rate2 clock cycle2 clock tick2 cycle time

#ignals may change at different speeds Dperations need to !e synchronised

Instruction e6ecution in discrete steps*(etch2 decode2 load and store2 arithmetic or logical

*Usually re3uire multiple clock cycles per instruction

Pipelining gives simultaneous e6ecution ofinstructions

#o2 clock speed is not the "hole story


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S1stem Cloc"


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Instruction E4ecution ate

Millions of instructions per second -MIP#.

Millions of floating point instructions per

second -M(5DP#. Feavily dependent on instruction set2

compiler design2 processor

implementation2 cache @ memoryhierarchy


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&enchmar"s

Programs designed to test performance

4ritten in high level language*Porta!le

8epresents style of task*#ystems2 numerical2 commercial

Easily measured

4idely distri!uted

E?g? #ystem Performance Evaluation Corporation-#PEC.*CPU/00) for computation !ound

$: floating point programs in C2 CJJ2 (ortran

$/ integer programs in C2 CJJ

' million lines of code

*#peed and rate metrics #ingle task and throughput


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SPEC Speed 'etric

#ingle task 7ase runtime defined for each !enchmark using

reference machine 8esults are reported as ratio of reference time to

system run time*Trefi e6ecution time for !enchmark i on reference

machine* i

Dverall performance calculated !y averagingratios for all $/ integer !enchmarks*Use geometric mean

Appropriate for normaliGed num!ers such as ratios


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SPEC ate 'etric

Measures throughput or rate of a machine carrying out anum!er of tasks

Multiple copies of !enchmarks run simultaneously* Typically2 same as num!er of processors

8atio is calculated as follo"sK* Trefi reference e6ecution time for !enchmark i

* N num!er of copies run simultaneously

* processors until completion of all copies of program

* Again2 a geometric mean is calculated


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Amdahl)s *a+

ene Amdahl AM,A):Q

Potential speed up of program using

multiple processors Concluded thatK

*Code needs to !e paralleliGa!le

*#peed up is !ound2 giving diminishing returnsfor more processors

Task dependent

*#ervers gain !y maintaining multipleconnections on multiple processors

*,ata!ases can !e split into parallel tasks


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Internet esources

httpK>>"""?intel?com>

*#earch for the Intel Museum

httpK>>"""?i!m?com httpK>>"""?dec?com

Po"erPC Intel ,eveloper Fome

f


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eferences

AM,A): Amdahl2 ?

02_computer evolution and performance [compatibility mode]

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